Pulsed Wordline Underdrive for SRAM Stability at Low Voltage
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Solution Overview
Problem
The reduction of supply voltage in SRAM cells leads to instability due to decreased static noise margin and write margin, causing data flipping issues, and existing wordline underdrive techniques result in decreased cell current and operational frequency.
Innovation Solution
A pulsed wordline underdrive assist circuit is introduced, which applies a series of pulses between the leading and trailing edges of the wordline signal, causing the voltage to fall and rise within a range greater than ground voltage, allowing for configurable pulse duration and interval, to enhance stability and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is reduced to lower power consumption, then energy efficiency improves, but static noise margin and write margin decrease causing data instability
Solution Approach 1:
The patent applies periodic pulsed underdrive signals to the wordline during the read operation. These pulses are applied at specific intervals between the leading and trailing edges of the wordline signal to maintain stability without requiring continuous voltage reduction. The pulsed action provides periodic reinforcement of the storage node voltages, enabling stable operation at reduced supply voltages while maintaining data integrity.
Solution Approach 2:
The patent dynamically changes the wordline voltage parameter by applying controlled underdrive pulses that temporarily reduce the voltage below the nominal level. This parameter modulation allows the circuit to operate stably at reduced supply voltages by adjusting the effective wordline voltage during critical operation periods, thereby improving power efficiency without sacrificing reliability.
2Reliability
If continuous wordline underdrive is applied to maintain stability at low supply voltage, then data stability improves, but cell current decreases and operational frequency is reduced
Solution Approach 1:
Instead of continuous underdrive, the patent employs periodic pulsed underdrive signals applied only during the read operation window. The pulses are timed to occur between the leading and trailing edges of the wordline signal, providing stability reinforcement only when needed. This periodic approach maintains data stability while allowing the circuit to operate at full speed during other phases, thus preserving operational frequency.
Solution Approach 2:
The patent dynamically adjusts the wordline voltage by applying underdrive pulses only during the read operation rather than maintaining a continuously reduced voltage. This dynamic control allows the circuit to switch between stable read operation mode and full-speed operation mode, optimizing both reliability and productivity based on the operational phase.
3Area of stationary object
If smaller transistor devices are used to reduce die area, then manufacturing cost and area improve, but variation and stability concerns increase
Solution Approach 1:
The patent applies preliminary anti-action by introducing underdrive pulses that counteract the destabilizing effects of small transistor variation before data flipping can occur. The pulses are timed to provide reinforcement during the read operation, preemptively compensating for the reduced noise margin inherent in smaller transistor devices, thus maintaining stability without requiring larger transistors.
Solution Approach 2:
The patent compensates for small transistor variation by dynamically adjusting the wordline voltage parameter through pulsed underdrive. This parameter modulation provides additional stability margin that offsets the increased variation in smaller transistor devices, enabling reliable operation with minimized die area.
Data Source
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Figure 5~7A
AI summary
A wordline coupled to a memory cell (12) is selected in connection with performing a read/write operation at the memory cell (12). A wordline signal is asserted on the selected wordline. The assertion of the wordline signal has a leading edge and a trailing edge and, between the leading edge and trailing edge, a series of wordline underdrive pulses. Each wordline underdrive pulse causes a wordline voltage to fall from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level. The first and second voltage levels are both greater than a ground voltage of the memory cell.