Row Hammer Refresh Address Sequences for Memory Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory components decrease in size, the increased density of memory cells leads to data degradation in nearby cells due to repeated access, known as the 'row hammer' effect, where victim rows are affected differently based on their relationship to the aggressor row, necessitating tailored refresh rates.
Innovation Solution
The semiconductor device incorporates a refresh address control circuit that identifies and refreshes victim rows based on their physical relationship to the aggressor row, using different refresh rates for adjacent and non-adjacent rows to mitigate the row hammer effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to improve storage capacity, then more memory cells can be packed in smaller area, but data degradation in nearby cells increases due to row hammer effect
Solution Approach 1:
The patent implements different refresh rates for different victim rows based on their physical proximity to the aggressor row. Specifically, first victim rows (more proximate) are refreshed at a first refresh rate, while second victim rows (less proximate) are refreshed at a second refresh rate. This local differentiation addresses the varying degrees of data degradation caused by row hammer effects at different spatial locations, thereby maintaining data integrity while supporting high memory cell density.
2Device complexity
If uniform refresh rate is applied to all victim rows, then refresh control is simplified, but data degradation cannot be effectively mitigated for rows with different vulnerability levels
Solution Approach 1:
The patent differentiates refresh rates based on the physical relationship between victim rows and aggressor rows. First victim rows that are more proximate to the aggressor row are refreshed at a first refresh rate, while second victim rows that are less proximate are refreshed at a second refresh rate. This approach tailors the refresh control to the specific vulnerability of each row, effectively mitigating data degradation while maintaining manageable system complexity through structured address generation.
3Reliability
If refresh operations are performed frequently to prevent data degradation, then data integrity is maintained, but memory performance and access speed are reduced
Solution Approach 1:
The patent applies different refresh rates to different victim rows based on their proximity to the aggressor row. First victim rows (more proximate) receive more frequent refreshes at a first refresh rate, while second victim rows (less proximate) receive less frequent refreshes at a second refresh rate. This localized approach ensures data integrity for highly vulnerable rows while minimizing the performance impact on less vulnerable rows, thereby optimizing the balance between reliability and speed.
Solution Approach 2:
The patent performs refresh operations selectively on victim rows rather than uniformly on all memory rows. By applying refresh operations only to identified victim rows and using different refresh rates based on vulnerability, the system performs partial action rather than exhaustive action. This reduces the overall number of refresh operations, thereby minimizing the impact on memory access speed while still maintaining data integrity for the affected rows.
4Reliability
If all victim rows are refreshed at the same high rate, then data degradation is minimized, but energy consumption and operational overhead increase
Solution Approach 1:
The patent implements different refresh rates for different victim rows based on their physical proximity to the aggressor row. First victim rows (more proximate) are refreshed at a first refresh rate, while second victim rows (less proximate) are refreshed at a second refresh rate. This localized differentiation ensures that energy-intensive refresh operations are concentrated on the most vulnerable rows, thereby maintaining data integrity while minimizing overall energy consumption compared to uniform high-rate refreshing of all rows.
Data Source
AI summary
Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.