Semiconductor Memory Device With Dummy Bit Section Timing Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high speed performance while minimizing the number of circuit elements, particularly in adapting to characteristic variations of memory cells, which can lead to errors in memory access due to inadequate timing adjustments.
Innovation Solution
The implementation of a semiconductor memory device with write and read dummy bit sections using dummy cells that mimic the characteristics of memory cells, allowing for timing control through complementary bit lines and timing control circuits to deselect word lines, thereby simplifying the circuit and improving signal consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells coupled to one word line and bit line is increased to increase memory capacity, then memory capacity increases, but the time required for selecting a memory cell becomes longer
Solution Approach 1:
The memory device is divided into multiple memory mats, where each mat contains a limited number of memory cells (e.g., 256×256) that can be selected within one clock cycle. This segmentation allows the system to achieve high memory capacity through multiple mats while maintaining fast selection speed within each individual mat.
2Adaptability or versatility
If timing adjustment circuits with dummy cells are provided to compensate for characteristic variation, then adaptability to characteristic variation improves, but the number of circuit elements increases
Solution Approach 1:
Dummy cells are created as simplified copies of actual memory cells, containing only the necessary components to replicate the timing characteristics. These dummy cells are used in timing adjustment circuits to compensate for variations in real memory cells without requiring complete replicas, thus reducing the number of circuit elements.
3Adaptability or versatility
If multiple dummy bit lines are provided to make the system adaptive to characteristic variation, then adaptability improves, but the number of dummy bit lines and circuit elements increases
Solution Approach 1:
Multiple dummy bit lines are merged into a single dummy bit line by connecting them together. The dummy cells are configured to sense changes on this combined dummy bit line, allowing the system to maintain adaptability to characteristic variation while reducing the number of separate dummy bit lines required.
Data Source
AI summary
This invention provides a semiconductor memory device with enhanced speed performance or enabling timing adjustment reflected in characteristic variation of memory cells, adapted to suppress an increase in the number of circuit elements. A write dummy bit section comprises a first dummy line and a second dummy line corresponding to complementary bit lines and a plurality of first dummy cells formed to be similar in shape to static memory cells, wherein a write current path is coupled between the first dummy line and the second dummy line. In the write dummy bit section, one voltage level is input to the first dummy line through driver MOSFETs in relation to write signal inputs to the static memory cells and a signal change in the second dummy line precharged at the other voltage level is sensed and output. A timing control circuit deselects a word line selected by an output signal from the write dummy bit section.