Semiconductor Memory Noise Generating Block for Test Mode Consistency
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Solution Overview
Problem
The difference in noise levels between wafer test and packaging test modes in semiconductor memory apparatuses leads to increased defects due to varying test conditions, as the amount of noise generated in the compress test mode differs from that in the normal mode.
Innovation Solution
A semiconductor memory apparatus with a noise generating block that includes a command decoder, control unit, and noise generating unit, which generates a noise test control signal to create a noise environment equivalent to the normal mode during testing, using a delay unit and current generating units, including transistors, to control and produce noise levels similar to those in normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compress test mode is used to improve time efficiency, then testing speed is improved, but noise level differs from normal mode causing increased defects
Solution Approach 1:
A noise generating block is introduced as an intermediary component between the control unit and memory banks. This block generates artificial noise signals that mimic the noise environment of normal mode operation, thereby mediating the test conditions to ensure accurate defect detection while maintaining the efficiency benefits of compress test mode.
Solution Approach 2:
The invention dynamically changes the noise level parameter during testing by controlling the noise generating block to produce different noise intensities. This allows the test system to simulate various operating conditions and ensure that defects are detected accurately under noise conditions similar to normal mode operation.
2Loss of time
If wafer test step uses compress test mode, then time efficiency is improved, but noise environment differs from packaging test mode
Solution Approach 1:
The noise generating block operates dynamically during the test process, adjusting its noise generation based on the test mode and environmental conditions. This dynamic operation allows the system to maintain consistent noise environment characteristics across different testing stages while preserving the time efficiency benefits of compress test mode.
Solution Approach 2:
The control unit receives feedback about the test environment and adjusts the noise generating block accordingly. This feedback mechanism ensures that the noise environment remains consistent between wafer test and packaging test modes, eliminating the stability issue while maintaining testing efficiency.
3Adaptability or versatility
If operating frequency is changed between wafer test and packaging test, then testing flexibility is improved, but noise level difference increases
Solution Approach 1:
The noise generating block is controlled to adjust its noise output parameters in response to changes in operating frequency. This allows the system to maintain consistent noise levels across different frequency conditions, preserving testing flexibility while eliminating the harmful noise level differences between wafer and packaging test stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the percentage of defects by creating a consistent noise environment across test modes, improving reliability by matching noise levels between wafer test and packaging test conditions.
Implementation Method 1
a current generating unit that generates a current between a first voltage terminal and a second voltage terminal according to the input of the noise test control signal that is supplied from the delay unit
Data Source
AI summary
Disclosed are a semiconductor memory apparatus and a method of testing the same. The semiconductor memory apparatus includes memory banks, each of which includes a plurality of memory cells, a peripheral circuit unit that includes a plurality of circuit groups around the memory banks, and a noise generating block that is disposed in the peripheral circuit unit and selectively applies a noise to the memory banks in a test mode.