Magnetic Memory Device Wiring Structure Void Prevention
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Solution Overview
Problem
Magnetic memory devices face challenges in achieving improved product reliability, particularly in the design and structure of wiring and electrode configurations within the memory cell array, which can lead to issues such as void formation and reduced reliability of reference resistors.
Innovation Solution
The magnetic memory device incorporates a specific stacking of insulating layers and wiring structures, including a first and second upper insulating layer, a mold layer, and distinct wiring and bit line structures, with a lower electrode contact between certain wiring structures, and MTJ structures, to enhance the reliability of the memory device and reduce void formation in the reference resistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional wiring structure with lower electrode contact between all wiring structures is used, then electrical connectivity is achieved, but void formation occurs and reliability of reference resistors deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the wiring structure into two distinct types: reference wiring structures that include lower electrode contacts and bit line wiring structures that exclude them. This localized differentiation eliminates void formation in the reference resistor region while maintaining necessary electrical connectivity in bit line regions, thereby improving reference resistor reliability without compromising overall device functionality.
Solution Approach 2:
The wiring structure is segmented into separate reference wiring structures and bit line wiring structures with distinct configurations. Reference wiring structures include lower electrode contacts for proper electrical connection, while bit line wiring structures intentionally exclude lower electrode contacts to prevent void formation. This segmentation allows each wiring type to be optimized for its specific function, resolving the contradiction between connectivity and void prevention.
2Productivity
If wiring structures are closely spaced to increase density, then device integration is improved, but manufacturing precision and reliability deteriorate due to void formation
Solution Approach 1:
By applying different structural qualities to different wiring types, the patent enables closer spacing of bit line wiring structures (which lack lower electrode contacts and thus avoid void formation) while maintaining adequate spacing for reference wiring structures. This local differentiation allows higher overall integration density without sacrificing manufacturing precision in critical reference resistor regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability of the magnetic memory device by minimizing voids in the reference resistor and enhancing the overall performance and stability of the memory cell array.
Implementation Method 1
a resistance change (MRAM) of a MTJ (Magnetic Tunnel Junction) thin film depending on a magnetization state of a ferromagnetic material
Data Source
AI summary
A magnetic memory device includes first and second upper insulating layers and a first mold layer sequentially stacked on a first substrate region; a first primary and first secondary wiring structure spaced apart in a first direction in the first upper insulating layer; a second wiring structure on the first primary wiring structure and a reference wiring structure on the first secondary wiring structure, in the second upper insulating layer; a first structure on the second wiring structure; a second structure on the reference wiring structure; a lower electrode contact between the second wiring structure and the first structure, and not between the reference wiring structure and the second structure, in the first mold layer; a bit line structure on the first structure; and a reference bit line structure on the second structure. The first and second structure include a lower electrode, MTJ structure, intermediate electrode, and upper electrode.