Semiconductor Memory Device Low-Frequency Test via Clock Divider

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Solution Overview

Problem

Current semiconductor memory device testing methods require separate test apparatuses for high-frequency and low-frequency operations, leading to increased testing costs due to the inability to detect defects present only in low-frequency environments using high-frequency test apparatuses.

Innovation Solution

A semiconductor memory device and method that enable low-frequency testing even when a high-frequency external clock signal is provided, utilizing a multi-step data input/output circuit, normal-frequency and low-frequency clock units, and a command interpreter to generate internal clock signals for both high-frequency and low-frequency operations, allowing for testing with a single high-frequency test apparatus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a high-frequency external clock signal is used for testing, then high-frequency operation performance can be tested, but low-frequency operation defects cannot be detected

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtesting frequency range
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic frequency adjustment by introducing a frequency divider that can operate in different modes. The command interpreter detects test mode signals and activates the frequency divider to reduce the external clock frequency, enabling the same hardware to adapt between high-frequency and low-frequency testing without requiring separate test apparatuses for each frequency range

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operating frequency parameter dynamically based on test requirements. By incorporating a frequency divider that can be activated during test mode, the system transitions from fixed high-frequency operation to variable frequency operation, allowing comprehensive defect detection across both high-frequency and low-frequency conditions using a single test apparatus

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If separate test apparatuses are used for high-frequency and low-frequency testing, then comprehensive defect detection is achieved, but testing cost increases considerably

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtest apparatus configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent makes the semiconductor memory device universally testable by enabling it to function as both a high-frequency device and a low-frequency device during testing. The frequency divider and command interpreter work together to allow the same device to be tested across different frequency ranges using a single high-frequency test apparatus, eliminating the need for separate low-frequency test equipment

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables the device to self-adjust its operating frequency during testing by incorporating the frequency divider and command interpreter within the device itself. The device automatically detects test mode signals and activates the appropriate frequency division, making the testing process self-contained and eliminating the need for external frequency adjustment equipment

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7551499B2Semiconductor memory device capable of performing low-frequency test operation and method for testing the same
Publication Date: 2009.06.23 SAMSUNG ELECTRONICS CO LTD
  • US7551499B2 patent drawing
  • US7551499B2 patent drawing
  • US7551499B2 patent drawing

AI summary

A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input. The method for testing the semiconductor memory device comprises: interpreting a control command from a plurality of external control signals and generating a low-frequency operation control signal when an MRS command included in the control command designates a write and read test operation; when a write command is input as the control command, converting the write command into a low-frequency write command in response to the low-frequency operation control signal, generating an internal low-frequency clock signal in response to the low-frequency operation control signal, and performing a low-frequency write operation based on the internal low-frequency clock signal; and buffering an external clock signal to generate an internal normal-frequency clock signal and, when a read command is input as the control command, performing a read operation based on the internal normal-frequency clock signal in response to the read command.