Semiconductor Memory Device Segmented Array Control
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Solution Overview
Problem
Highly integrated resistance variation type memory devices experience power noise and malfunction due to large charging currents generated by parasitic capacitance, especially as integration levels increase.
Innovation Solution
A nonvolatile semiconductor memory device with a control circuit that selectively applies voltage to memory cells, accumulating electric charge in parasitic capacitance of unaccessed unit cell arrays at different times to reduce the maximum charging current and stabilize noise levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistance variation type memory is integrated at higher levels to achieve higher integration, then device integration level is improved, but charging current increases causing power noise and malfunction
Solution Approach 1:
The memory device is divided into multiple independent unit cell arrays (first unit cell array, second unit cell array, etc.). The control circuit selectively activates only the required unit cell array for each operation, while keeping other arrays in a non-active state. This segmentation isolates the charging current generation to only the active array, preventing simultaneous charging currents from multiple arrays that would cause power noise and malfunction.
2Ease of operation
If voltage is applied to unselected memory cells to apply reverse bias, then memory cell operation is enabled, but parasitic capacitance charging current increases
Solution Approach 1:
The control circuit applies reverse bias voltage to unselected memory cells in advance before the actual read/write operation. This preliminary action prepares the memory cells for proper operation by establishing the required bias conditions, while the segmented array structure ensures that this preliminary biasing is applied only to the specific unit cell array that will be accessed, minimizing overall charging current.
3Speed
If all unit cell arrays are accessed simultaneously, then operation speed is improved, but power noise increases due to simultaneous charging currents
Solution Approach 1:
The memory device is divided into multiple independent unit cell arrays that can be independently controlled. The control circuit selectively activates only the required unit cell array for each operation, while keeping other arrays in a non-active state. This segmentation isolates the charging current generation to only the active array, preventing simultaneous charging currents from multiple arrays that would cause power noise and malfunction.
Solution Approach 2:
The control circuit implements time-multiplexed operation where different unit cell arrays are activated in sequential time periods rather than simultaneously. Each array is accessed during its designated time window, and the control circuit switches between arrays periodically. This periodic activation pattern maintains operational throughput while ensuring that charging currents from different arrays do not overlap, thereby eliminating power noise issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers the maximum charging current and stabilizes current change rates, thereby reducing noise and preventing malfunctions in high-integration memory devices.
Implementation Method 1
a parasitic capacitance of the memory cell included in a first unit cell array that is said specific unit cell array and not accessed at the first time, while on the other hand, accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a second unit cell array that is said specific unit cell array other than said first unit cell array and not accessed at the second time after the passage of a predetermined time from said first time
Data Source
AI summary
A nonvolatile semiconductor memory device having a plurality of unit cell arrays having memory cells each containing a first wiring and a second wiring intersecting each other, and a variable resistive element arranged at each intersection of said first wiring and said second wiring and electrically rewritable to nonvolatilely store a resistance value as data, characterized by comprising: a control circuit for applying a predetermined voltage to said memory cell in selectively accessing said memory cell; wherein said control circuit accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a first unit cell array that is said specific unit cell array and not accessed at the first time, while on the other hand, accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a second unit cell array that is said specific unit cell array other than said first unit cell array and not accessed at the second time after the passage of a predetermined time from said first time.