FeSRAM Cell Non-Volatile Read via Segmented Transistors
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Solution Overview
Problem
Ferroelectric memory circuits face challenges with high programming voltages reducing endurance and requiring larger circuit elements, leading to slower read and write speeds and lower data densities compared to conventional SRAMs, while volatile operations necessitate frequent refreshing to prevent data loss.
Innovation Solution
The implementation of FeSRAM cells with cross-coupled inverters and ferroelectric capacitors that receive programming voltages through access transistors, allowing non-volatile states to be maintained without exposing SRAM transistors to high programming voltages, enabling the use of low-voltage transistors and reducing the silicon footprint to match conventional SRAMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If high programming voltage is applied to ferroelectric capacitor for non-volatile storage, then non-volatile data retention is achieved, but transistor endurance decreases and circuit size increases
Solution Approach 1:
The patent divides the memory cell into two distinct transistor types: access transistors that handle only low-voltage volatile operations, and a separate high-voltage programming transistor dedicated to non-volatile programming. This segmentation allows each transistor to be optimized for its specific voltage range, preventing high programming voltages from degrading the access transistors while maintaining non-volatile storage capability.
Solution Approach 2:
The patent introduces a specialized high-voltage programming transistor as an intermediary component between the control logic and the ferroelectric capacitor. This intermediary transistor is specifically designed to withstand high programming voltages and transfer them to the capacitor without exposing the standard access transistors to damaging voltage levels.
2Duration of action of stationary object
If high programming voltage is used for non-volatile programming, then persistent storage is achieved, but read and write speeds decrease
Solution Approach 1:
The patent separates programming operations from read/write operations by dedicating different transistors to each function. Access transistors handle fast low-voltage read/write operations, while a separate high-voltage transistor handles slower programming operations. This segmentation allows read/write operations to proceed at high speeds without being bottlenecked by the slower high-voltage programming process.
3Duration of action of stationary object
If high programming voltage is applied to program ferroelectric capacitor, then non-volatile states are achieved, but silicon footprint increases
Solution Approach 1:
The patent combines the high-voltage programming transistor with the existing access transistors in a shared layout, utilizing the same interconnect structures and capacitor plates. By merging the programming function into the existing memory cell architecture rather than adding completely separate high-voltage circuitry, the patent achieves non-volatile capability with minimal increase in silicon footprint.
4Duration of action of stationary object
If high programming voltage is used for non-volatile operations, then persistent storage is achieved, but SRAM transistor performance degrades
Solution Approach 1:
The patent segments the transistor population into access transistors optimized for low-voltage SRAM operations and a separate high-voltage programming transistor. This segmentation ensures that the access transistors maintain their original performance characteristics by never being exposed to high programming voltages, while the dedicated programming transistor handles the high-voltage operations.
Solution Approach 2:
The high-voltage programming transistor serves as an intermediary that isolates the sensitive access transistors from damaging high-voltage stress. This intermediary transistor is specifically designed with high-voltage tolerance and handles all high-voltage programming operations, protecting the access transistors from voltage-induced degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for comparable read and write speeds to conventional SRAMs while maintaining non-volatile states, reducing the need for frequent refreshing and achieving similar data densities without the stress of high programming voltages on SRAM transistors.
Implementation Method 1
Memory circuits using ferroelectric materials (e.g., lead zirconate Titanate (PZT)) have been proposed
Implementation Method 2
when used as a volatile memory cell, a programming voltage (e.g., Vcc such as 1.2 volts) that is much lower than the programming voltage for a non-volatile programmed state is applied across ferroelectric capacitor 100
Data Source
AI summary
A FeSRAM cell includes (a) first and second inverters between a power supply voltage and a ground reference cross-coupled to each other, the first and second cross-coupled inverters providing first and second data terminals; (b) first and second select transistors respectively coupled to the first and second data terminals to control access to the first second data terminals; and (c) first and second ferroelectric capacitors coupled between a first plate line and respectively the first and second data terminals, the first plate line receiving a negative programming voltage having a magnitude greater than the power supply voltage to allow programming one of the first and second ferroelectric capacitors into a first non-volatile programmed state.