Master/Slave Identification in Stacked Memory via TSV

Solution Overview

Problem

High density memory architecture with stacked memory dies complicates master/slave die identification and chip select signal propagation, requiring additional die area for detection functions.

Innovation Solution

A laddered chip select architecture and master/slave identification circuits that use chip select nodes and through-substrate vias to propagate and detect chip select signals, allowing for efficient identification of master and slave memory units without complex coupling between them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional master/slave identification circuits are used in stacked memory dies, then master/slave die identification and chip select signal detection functions are achieved, but additional die area is required and device complexity increases

Engineering Contradiction:

Improvemaster/slave die identificationVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The chip select detection circuit is designed to perform multiple functions: it detects chip select signals, identifies master/slave status, and determines response priority. By making the circuit universal, the patent eliminates the need for separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining reliable master/slave identification in stacked memory dies

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the chip select signal detection function with the master/slave identification function into a single integrated circuit. The chip select detection circuit merges the roles of signal detection, master/slave status identification, and response priority determination, reducing the number of separate components needed and simplifying the overall device architecture

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If additional detection functions are added to identify master/slave dies, then master/slave identification is improved, but die area increases

Engineering Contradiction:

Improvemaster/slave die identificationVSAvoiddie area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The chip select detection circuit is designed to perform multiple functions: it detects chip select signals, identifies master/slave status, and determines response priority. By making the circuit universal, the patent eliminates the need for separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining reliable master/slave identification in stacked memory dies

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the chip select signal detection function with the master/slave identification function into a single integrated circuit. The chip select detection circuit merges the roles of signal detection, master/slave status identification, and response priority determination, reducing the number of separate components needed and simplifying the overall device architecture

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If complex coupling between memory units is used for master/slave identification, then identification accuracy is improved, but ease of manufacture decreases

Engineering Contradiction:

Improvemaster/slave identificationVSAvoidease of manufacture

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the master/slave identification into a standardized detection circuit that can be independently implemented in each memory die. By using through-substrate vias to connect identical detection circuits across stacked dies, the patent simplifies manufacturing compared to complex custom coupling schemes, while still achieving reliable master/slave identification through the standardized interface

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9305625B2Apparatuses and methods for unit identification in a master/slave memory stack

Publication Date: 2016.04.05 MICRON TECHNOLOGY INC

AI summary

Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.