Dual Rail SRAM Level Shifter for PMOS Leakage Control
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Solution Overview
Problem
Dual rail SRAM circuits face issues with PMOS transistor leakage due to insufficient voltage headroom, leading to current leakage during read/write operations and standby mode, as the PMOS transistor does not fully turn off when connected to different power supply voltages, limiting the minimum power supply voltage and affecting static noise margin (SNM).
Innovation Solution
Incorporating a level shifter that converts the input signal from Vdd to CVdd, ensuring the gate voltage of PMOS transistors is higher than the source voltage, effectively turning off the PMOS transistors and preventing current leakage by using PMOS transistors in the word line driver and precharge control circuits, thereby maintaining sufficient SNM and reducing dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If dual rail SRAM is used to avoid SNM limitation at lower voltage, then voltage headroom is improved, but PMOS transistor leakage increases due to insufficient voltage headroom causing current leakage during read/write operations and standby mode
Solution Approach 1:
A level shifter circuit is introduced as an intermediary component between the input signal and the PMOS transistor gate. The level shifter converts the input signal voltage to an appropriate level that ensures the gate voltage is higher than the source voltage, enabling proper PMOS turning off while maintaining dual rail operation for SNM improvement
Solution Approach 2:
The patent changes the voltage parameter at the PMOS gate by using a level shifter that outputs a voltage level suitable for the PMOS transistor's operating conditions. This parameter change ensures that the gate voltage is sufficiently higher than the source voltage, allowing the PMOS to fully turn off and preventing leakage current
2Power
If PMOS transistor gate voltage is lowered to match lower supply voltage, then power consumption is reduced, but PMOS transistor cannot fully turn off causing current leakage
Solution Approach 1:
The level shifter acts as a mediator that receives the low-voltage input signal and converts it to a higher voltage level appropriate for driving the PMOS transistor gate. This ensures the PMOS can fully turn off even when the supply voltage is reduced, maintaining reliable switching performance while enabling lower power consumption
3Use of energy by moving object
If lower supply voltage is used to reduce dynamic power consumption, then energy efficiency is improved, but static noise margin decreases limiting the minimum power supply voltage
Solution Approach 1:
The patent segments the voltage supply into two distinct rails: a lower supply voltage for reducing dynamic power consumption and a higher supply voltage for maintaining sufficient static noise margin. The level shifter enables this segmentation by converting signals from the lower voltage domain to the higher voltage domain where needed, allowing both low power consumption and high SNM to coexist
Data Source
AI summary
A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control.