High Bandwidth Memory Interconnect Routing via Redistribution Layer Segmentation
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Solution Overview
Problem
High bandwidth memory stack devices with tightly packed contacts face challenges in flexible signal routing and increased costs due to the use of expensive package interconnect technologies like silicon interposers, which limit flexibility and cause placement conflicts with CPUs and GPUs.
Innovation Solution
Implementing a redistribution layer that merges memory channels and I/O signal paths, allowing for reduced active connections and increased contact pitches, thereby enabling more flexible interconnect routing and reducing signal interference and heat issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If expensive package interconnect technologies like silicon interposers are used to handle tightly packed contacts, then the contact pitch issue is resolved, but the device complexity and cost increase
Solution Approach 1:
The patent segments the I/O contacts into two distinct groups: first I/O contacts with a first pitch and second I/O contacts with a second pitch. This segmentation allows each group to be handled differently in the redistribution layer, enabling flexible routing without requiring expensive silicon interposer technologies. The segmentation resolves the contact pitch issue by allowing varied pitch requirements to be met through logical grouping rather than physical redesign.
Solution Approach 2:
The patent introduces a dimensional approach by routing signals through multiple layers (first redistribution layer and second redistribution layer) and using both first and second I/O contacts for signal transmission. This multi-dimensional routing strategy enables the system to achieve flexible interconnect routing and reduced signal interference without increasing contact pitch or using complex package interconnect technologies.
2Adaptability or versatility
If the number of active connections is reduced to increase flexibility, then routing flexibility improves, but signal transfer capability may be compromised
Solution Approach 1:
The patent merges the functionality of multiple I/O contacts into fewer active connections by strategically selecting which contacts to activate based on signal routing requirements. The logic layer and redistribution layers combine multiple signal paths into consolidated routes that use fewer active connections, achieving routing flexibility while maintaining signal transfer capability through intelligent signal consolidation and path merging.
Solution Approach 2:
The patent changes the parameter of active connection count by dynamically determining which I/O contacts are active based on the mode of operation. By adjusting the number and selection of active connections according to signal routing needs, the system achieves routing flexibility without compromising signal transfer capability, as the active connections are strategically chosen to maintain full functionality.
3Quantity of substance
If tightly packed contacts are used to provide high bandwidth memory density, then memory density increases, but signal interference and heat issues worsen
Solution Approach 1:
The patent segments I/O contacts into first and second groups with different pitch characteristics, allowing signals to be routed through separated contact groups. This spatial segmentation reduces signal interference between adjacent signals and improves heat dissipation by creating separation zones, while maintaining high memory density through the segmented contact structure.
Solution Approach 2:
The patent resolves signal interference and heat issues by routing signals through multiple vertical layers (first and second redistribution layers) rather than confining all signals to a single plane. This vertical dimensionality separates signal paths that would otherwise be closely packed, reducing mutual interference and improving thermal management while preserving the high density achieved through vertical stacking.
Data Source
AI summary
Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.