Data Verification Device for DRAM Signal Integrity

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Solution Overview

Problem

As Dynamic Random Access Memory (DRAM) becomes smaller and faster, ensuring accurate data recognition in the internal signal paths is critical, particularly with the introduction of Decision Feedback Equalization (DFE) options that vary by vendor, necessitating a method to verify write performance and signal integrity.

Innovation Solution

A data verification device and method that writes high and low frequency sequence data to a memory, compares voltage values, and outputs maximum voltage values to determine DFE strength and trend, using unique topo sequence methodologies to assess DDR5 Receiver performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high frequency sequence data is written to verify write performance, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improvewrite performance verification accuracyVSAvoidverification process complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The verification process is segmented into multiple frequency components (high frequency and low frequency sequences) that can be independently tested and analyzed. This allows precise measurement of different aspects of write performance while managing complexity through modular testing approaches.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes frequency parameters to verify write performance at different operating conditions. By testing both high and low frequency sequences, the system achieves comprehensive measurement precision across the operating range without requiring a single overly complex verification mechanism.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If multiple voltage comparisons are performed to determine maximum voltage, then measurement precision is improved, but loss of time increases

Engineering Contradiction:

Improvevoltage measurement accuracyVSAvoidverification time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary voltage comparisons during the write verification process by comparing first and second voltage values to determine maximum voltage. This preliminary action integrates measurement into the existing verification workflow, achieving precise voltage measurement without significant time penalty.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If DFE strength and trend are distinguished using topo sequence methodologies, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvesignal integrity verificationVSAvoidverification system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses voltage values as intermediary measurements to determine DFE strength and trend. By comparing first and second voltage values obtained from high and low frequency sequences, the system reliably assesses signal integrity without requiring direct complex DFE analysis, thus managing system complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250308578A1Data verification device and data verification method

Publication Date: 2025.10.02 NAN YA TECH

AI summary

A data verification device includes a processor. The processor is configured to perform following steps: writing a first high frequency sequence data to a memory to obtain a first voltage value; writing a second high frequency sequence data to the memory to obtain a second voltage value; comparing the first voltage value and the second voltage value to obtain a first maximum voltage value; and outputting the first maximum voltage value. The first high frequency sequence data includes a first sub data having a first logic value of 0101.