Cantilever NEM Decoder Circuit for Dense Memory Array Access
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Solution Overview
Problem
Existing semiconductor technologies face challenges in efficiently accessing individual memory cells in a two-dimensional array due to the large device area required for word line decoders and bit line decoders, and there are variations in decoupling capacitance that impact performance.
Innovation Solution
Incorporation of cantilever nanoelectromechanical (NEM) devices at the interconnect level to provide bit line and word line decoders, using hybrid logic gates for activation, with minimal use of complementary metal-oxide-semiconductor (CMOS) devices, allowing random access of memory cells and reducing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional CMOS-based word line decoders and bit line decoders are used, then memory cell access functionality is achieved, but large device area is required
Solution Approach 1:
The patent replaces traditional CMOS electronic decoders with nanoelectromechanical (NEM) switch-based decoders. The NEM switches use mechanical movement of nanoscale beams to open or close circuit paths, substituting electronic switching mechanisms. This mechanical approach at the nanoscale enables decoder functionality with significantly reduced area compared to conventional CMOS implementations, directly resolving the contradiction between achieving memory access functionality and minimizing decoder area.
Solution Approach 2:
The patent transitions from planar CMOS device architecture to three-dimensional NEM switch structures with movable beams that operate in the vertical dimension. The NEM switches utilize out-of-plane beam deflection to control circuit connectivity, adding a vertical dimension to the switching mechanism. This dimensional transition enables higher density and reduced area footprint for the decoder circuitry while maintaining full memory access functionality.
2Reliability
If decoupling capacitance is increased to improve performance, then signal stability is improved, but device area and complexity increase
Solution Approach 1:
The patent utilizes the inherent mechanical parameters of NEM switches, specifically the movable beam structures, to provide parasitic capacitance that serves as decoupling capacitance. By adjusting the geometry, material composition, and positioning of the NEM switch beams, the effective capacitance values can be tuned to provide necessary signal stability without requiring separate dedicated capacitor structures. This parameter optimization enables achieving signal stability with minimal additional area.
Solution Approach 2:
The patent makes the NEM switch structures serve multiple functions: they act as both the switching elements for memory cell access and simultaneously provide the decoupling capacitance needed for signal stability. The movable beams of the NEM switches inherently possess capacitive characteristics that can be leveraged for signal conditioning. This multi-functionality eliminates the need for separate capacitance elements, reducing overall device area while maintaining signal stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient random access of memory cells with reduced area usage and performance validation, minimizing the need for CMOS devices and optimizing decoupling capacitance variations.
Implementation Method 1
Nanoelectromechanical devices may control signals based on nanoscale movement of mechanical elements under electrical bias
Data Source
AI summary
A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.