Cap Layer and Sidewall Spacer for HKMG Through-Hole Precision
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Solution Overview
Problem
The reliability and stability of the fabrication process for high-K metal gate (HKMG) structures in semiconductor manufacturing are compromised due to position shifts during photolithography overlay, leading to position errors and potential damage to the metal gate surface during etching processes.
Innovation Solution
A method involving the formation of a metal gate structure with a cap layer and protective sidewall spacer, where the cap layer serves as an etching mask to control the thickness of the first dielectric layer and prevent exposure of the metal gate surface, and the sidewall spacer aids in forming conductive vias without bridging issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography overlay is used to form through-holes, then through-hole formation is enabled, but position shifts occur leading to position errors and potential damage to the metal gate surface
Solution Approach 1:
A cap layer is introduced as an intermediary protective element between the etching process and the metal gate surface. This cap layer absorbs the position shifts during photolithography overlay, preventing direct damage to the metal gate while still enabling through-hole formation. The cap layer acts as a buffer that mediates between the imprecise overlay process and the sensitive metal gate structure.
Solution Approach 2:
The cap layer is formed in advance before the through-hole etching process. This preliminary action ensures that the metal gate surface is protected before any etching occurs, preventing position errors from causing direct damage. The protective structure is prepared beforehand to anticipate and prevent potential harm during subsequent processing steps.
2Manufacturing precision
If the first dielectric layer is etched to form through-holes, then source/drain regions are exposed, but the metal gate surface may be exposed and damaged due to position shifts
Solution Approach 1:
The cap layer serves as a protective intermediary that remains in place during through-hole formation. It mediates between the etching process and the metal gate, allowing the first dielectric layer to be removed while the cap layer prevents the etch from reaching and damaging the metal gate surface, even when position shifts occur.
Solution Approach 2:
The cap layer provides beforehand cushioning protection for the metal gate surface. By having this protective layer in place prior to etching, the system is cushioned against the harmful effects of position shifts, ensuring that even if alignment is not perfect, the metal gate remains protected from direct exposure and damage.
3Reliability
If conventional gate-last process is used to form HKMG structure, then metal gate structure is achieved, but reliability and stability of fabrication process need improvement
Solution Approach 1:
The cap layer is introduced as an intermediary protective structure that enhances fabrication process reliability. While it adds a layer to the process structure, it significantly improves stability by preventing position errors and metal gate damage during through-hole formation, making the overall fabrication process more reliable and controllable.
Data Source
AI summary
A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.