Capacitance-to-Digital Conversion Circuit With Adaptive Range Shift
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Solution Overview
Problem
Existing capacitance-to-digital conversion circuits face challenges in balancing energy efficiency, precision, and robustness, particularly in harsh environments, due to limitations in dynamic range and high power consumption in SAR and DSM-based sensors.
Innovation Solution
A capacitance-to-digital conversion circuit incorporating a successive approximation unit, adaptive range-shift module, and digital-to-analog converters, which coarsely quantizes sensor signals, calculates compensation values, and adjusts analog signals to maintain optimal input ranges for delta-sigma modulators, thereby enhancing robustness and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If SAR-based capacitive sensors are used, then energy efficiency is improved, but measurement precision deteriorates
Solution Approach 1:
The patent divides the capacitive sensing system into multiple independent sensing units, each with its own readout circuit. This segmentation allows parallel operation of multiple SAR converters, improving overall precision through multiple measurements while maintaining low power consumption of individual units.
Solution Approach 2:
The patent implements preliminary calibration and offset compensation before actual measurements. By pre-characterizing parasitic capacitances and storing compensation values in lookup tables, the system eliminates the need for high-power real-time correction circuits, maintaining precision while preserving energy efficiency.
2Measurement precision
If DSM-based capacitive sensors are used, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic switching and sampling in the DSM architecture, where the delta-sigma modulator operates in discrete phases rather than continuous high-power operation. This periodic action reduces average power consumption while maintaining precision through oversampling and noise shaping.
Solution Approach 2:
The patent recovers and reuses reference voltages and calibration data across multiple measurement cycles. By maintaining calibrated reference values and reusing them instead of continuously recalibrating, the system preserves precision while significantly reducing power consumption.
3Reliability
If redundancy is increased between stages, then robustness is improved, but precision deteriorates
Solution Approach 1:
The patent performs preliminary offset calibration and stores compensation values before operation. This preliminary action eliminates the need for continuous redundancy margins, allowing the system to achieve both robustness (through pre-characterized compensation) and precision (by using full dynamic range for measurements).
Solution Approach 2:
The patent creates digital copies of calibration data and offset values that are stored and reused across multiple measurement cycles. These digital copies provide robustness without consuming additional analog dynamic range, thereby maintaining precision while ensuring reliable operation.
4Measurement precision
If redundancy is decreased between stages, then precision is improved, but robustness deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where calibration data and offset compensation values are continuously updated based on measured performance. This feedback loop ensures that the system maintains both high precision (by optimizing operating points) and robustness (by adapting to drift and environmental changes).
Solution Approach 2:
The system performs self-calibration and self-compensation using on-chip reference elements and stored calibration data. This self-service capability provides robustness without requiring external redundancy margins, allowing maximum precision while ensuring reliable operation through automated correction.
Data Source
AI summary
Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.