Analogue Conversion TRIZ Cases

Adding voltage feedback to current feedback gives the passive resonator enough freedom to realize arbitrary bandpass noise transfer functions.

A single-bit stream crosses the isolation barrier without framing, then is filtered back to multi-bit data for lower latency and EMI resilience.

Separating self-test and sensing paths in time helps this readout circuit suppress noise and avoid bulky high-order filters.

A reset phase drives the sampling capacitor to a data-independent charge, cutting kickback, glitches, and inter-symbol interference in ADC circuits.

Parallel sensor grouping with combiner feedback cuts position-estimation latency and improves SNR over sequential scanning.

Buffer-charged capacitor phases raise input impedance in a switched-capacitor amplifier without extra clocks, reducing power and preserving speed.

A delayed input and digital error-correction path improve CT ADC transfer-function estimation despite injection DAC mismatch and input signals.

Double sampling and thermometric reference switching cut input thermal noise in a Sigma-Delta integrator while preserving ADC power and area.

Time-interleaved data streams and ERS logic shape DAC mismatch errors while reducing idle tones, power use, and distortion.

A capacitor-free current-mode sigma-delta ADC cuts switching noise, power use, and area while speeding resistive memory readout.

Frequency-coded touch sensors share one signal path, enabling FFT-based readout for faster, denser robotic tactile sensing with lower latency.

A common-mode test signal exposes anti-aliasing filter mismatch, enabling PID tuning of resistors and capacitors to suppress differential error.

Differential sensing and sigma-delta noise shaping cut parasitic capacitance effects, speeding accurate touch location detection.

Charge-domain combiners, shift registers, and quantization enable direct image-sensor coupling with higher SNR and lower power.

A bias-compensated OTA pair and differential DAC improve common-mode rejection and cut THD+N in single-ended microphone ADCs.

A compensation filter corrects excess loop delay in a delta-sigma modulator, improving stability and SQNR while relaxing quantizer timing.

Passive error extraction and noise cancellation cut ADC power use while preserving signal-to-noise ratio and conversion bandwidth.

A VCO-based Delta-Sigma ADC converts the analog error signal into digital pulses, simplifying Class-D amplifier control while preserving accuracy.

A shared SAR DAC cuts capacitance, power, and area while calibrating excess loop delay compensation in continuous-time delta-sigma ADCs.

A preamplifier and resonator shape the noise transfer function to attenuate audio-band noise while improving modulator stability and power use.

A primary delta-sigma stage and residual error amplifier split ADC workload, improving speed and accuracy without demanding ultra-precise comparators.

A capacitor-based PWM observation circuit lets HIL systems measure duty cycle without high-frequency FPGA chips, cutting cost and processing load.

Force-and-correction compensates chopping-induced duty cycle and quantization noise errors in delta-sigma modulators while preserving stable input range.

A delayed, low-power feedback ADC lets a digital Class D driver process only error signals, cutting heat and extending battery life.

Dynamic scaling keeps quantizer ratios stable to cut quantization noise, extend dynamic range, and avoid audible pop transients.

Compensation currents derived from switch voltage drops correct DAC gain error and drift while preserving linearity with smaller switches.

A variable-frequency chop clock spreads offset in sigma-delta ADCs, suppressing fold-back tones while avoiding high-frequency noise penalties.

A thermometer-code intermediary and circular shift path cut delay and power in DWA-to-binary conversion above 2 GHz.

Adaptive range shifting compensates parasitics and interference in capacitance readout, improving robustness and efficiency in harsh environments.

Matched OTA biasing in a sigma-delta microphone ADC improves common-mode rejection and lowers THD+N without high current draw.

A controller switches microphone sigma-delta ADC modes to improve common-mode rejection on long wires while avoiding unnecessary power use.

Pulse-based error processing uses a counter and DAC to replace large external capacitors, enabling precise low-bandwidth IC compensation.

Phase freezing lets an oversampled oscillator-based converter cut jitter noise and power use while preserving SNR in compact low-power electronics.

Force-and-correction compensates delta-sigma modulator force errors to cut flicker noise without shrinking stable input range.

A digital feed-forward loop removes signal content before ADC feedback, cutting class D modulator power dissipation and heat.

A sigma-delta control circuit adapts quadrature cancellation outside the sensing band to preserve MEMS gyroscope sensitivity and avoid recalibration noise.

Distinct noise transfer functions across parallel sigma-delta channels decorrelate quantization noise while preserving signal quality and lowering DAC complexity.

Diode-connected transistor stacks create large signal delays without long inverter chains, cutting power use and die area.

A single-ended sigma-delta touch channel uses current balancing to raise SNR while cutting amplifiers, switches, capacitors, and channel size.

A digital pulse-counter-DAC loop replaces large compensation capacitors, enabling stable on-chip control with fewer parts and lower cost.

High-order polynomial interpolation generates PWM signals with free amplitude and phase selection while preserving phase continuity under carrier-frequency changes.

Chopping at the amplifier input and output shifts offset out of the signal path, improving delta-sigma integration accuracy and final output.

Lower-frequency, low-voltage digital beamforming cuts probe power and heat while preserving 2D and 3D ultrasound imaging.

Dynamic switching between high and zero output resistance cuts ADC power use while preserving audio fidelity and reducing transition artifacts.

Asynchronous demodulation with phase correction lets metal detectors use varied ADCs without synchronous hardware constraints.

Digital noise coupling and MASH conversion improve ADC SNR while avoiding higher power draw and instability from high-order loop filters.

Digital pulse generation, counting, and DAC conversion replace external capacitor loop compensation, improving precision, cost, and reliability.

Injected dither tones and DSP measure interleaving spurs in delta-sigma ADC DACs, enabling correction of clock-duty-induced SNR loss.

Delta-sigma test patterns calibrate DAC bit-cell amplitude and timing errors, cutting distortion and improving dynamic range.

Randomized DAC element calibration finds an optimal unary source order to cut nonlinearity and raise Sigma-Delta ADC SNDR without extra loop delay.

A split integer-fractional DAC architecture uses delta-sigma oversampling to cut pre-distortion complexity and power while correcting nonlinearity.

A correction word compensates coarse-fine feedback errors in a coarse-incremental ADC, improving accuracy with fewer integration cycles.

A digital chopper and filter replicate chopping folding error in delta-sigma modulators, then subtract it to suppress downfolded noise.

Delta-Sigma pulse density modulation drives field sequential color frames to cut display power while improving brightness, contrast, and saturation.

Offset capacitors and controllable switches cancel op-amp offset across conversion phases, improving ADC accuracy and efficiency.

Time-direction multiplexing sends abnormal-state signals on the normal isolator path, cutting detection delay and avoiding extra circuitry.

Correlation-based estimation and a replica DAC correct multi-bit sigma-delta mismatch non-linearity to preserve signal-to-noise ratio.

Correlation of an injected PRBS or dual-tone signal tunes sigma-delta resonators to keep notch frequency and SQNR stable across drift.

Feedback compensation sources or sinks current as terminal voltage shifts, balancing DAC transistor currents to reduce harmonics, noise, and distortion.

Preconfigured digital channels let one analog channel switch inputs without filter reset, cutting ADC delay and power use.

Feedforward capacitors and compensating zeros help continuous-time sigma-delta ADCs overcome parasitic-capacitance settling and stability limits.

Non-equidistant sample timing lets a delta-sigma ADC power down during unused OFDM intervals, cutting receiver energy use.

A decoupled mapping engine and linearization DAC correct multibit DAC mismatch without adding feedback-loop delay in high-speed sigma-delta ADCs.

High-order polynomial interpolation and dithering preserve phase continuity under carrier-frequency shifts while reducing harmonic distortion.

Code modulation on only the high-order delta-sigma bits cuts transmission noise and circuit area while preserving multi-bit audio quality.

Real-time ADC and reference-path coefficient updates correct board, temperature, voltage, and aging non-linearity without factory calibration.

A coupling capacitor blocks ambient-light DC offset so a TOF receiver can detect weak reflected pulses without saturation.

Windowed sinusoidal VCOM sensing and custom display-scan transitions reduce emissions while preserving SNR in automotive in-cell touch displays.

Delta-Sigma pulse density modulation replaces binary PWM to cut false contouring, lower display power, and preserve image quality.

Combining counter data with phase-difference conversion enables accurate frequency ratio measurement without divider switching complexity.

Nonlinear multi-bit feedback lets a sigma-delta ADC track rapid pulse transients and preserve waveform shape with realistic sampling rates.

A discrete 75/25 dither scheme cuts audio quantization noise penalty while keeping error variance constant and avoiding noise modulation.

Auto-zeroing with MASH readout suppresses water-droplet parasitic capacitance drift, preserving accurate pressure sensor signals.

Input shuffling and feedback compensation remove comparator offset differences in multibit ADCs, improving linearity and noise behavior.

Oversampling and noise shaping carry LTE, Wi-Fi, and 5G-NR signals in a low-bit stream while removing remote DAC and RF hardware.

Truncation error compensation lets a delta-sigma modulator cut DAC bit count and hardware complexity without degrading noise shaping.

A quantized feedback sigma-delta modulator removes common-mode control and reference currents to cut circuit noise and component count.

Non-recursive residue computation lets a digital delta-sigma modulator raise output sample rates while dynamically tuning the output frequency band.

Future-weighted additional signal selection suppresses re-quantization noise growth and preserves audio SNR when reducing PCM resolution.

Two switched-capacitor paths share one op-amp so sampling and integration run together, improving ADC resolution, SNR, and THD without more power.

Non-uniform quantization levels improve ANC sigma-delta SNR while reducing multiplier hardware, power use, and stability tradeoffs.

Measures high-frequency clock jitter by injecting a jittered tone into a CT-Delta-Sigma modulator and detecting SNR degradation without an external reference.

Dual feedback paths correct offset and drift in differential amplifiers, keeping common mode voltage stable and preserving dynamic range.

A switched differential integrator with reset switches cuts noise correlation, saves area, and improves capacitor mismatch robustness in sigma-delta modulators.

A two-stage sigma-delta modulator cuts output levels before the H-bridge, reducing saturation and power draw in low-impedance audio loads.

Noise-shaped delta-sigma RF digitization helps HFC links carry higher-order modulation over longer fiber spans with better nonlinear-noise tolerance.

A feedback limiter clips oversampled sigma-delta signals while pushing clipping noise out of the audio band, reducing in-band noise without extra filtering.

A test-signal feedback circuit tunes the SDM resonator to offset PVT variation, improving SNR and reducing EVM and noise.

A two-stage delta-sigma filtering scheme improves resolver synchronization by separating decimation from fine time-quantized interval processing.

A segmented series-parallel resistor network widens PGA gain selection while cutting power, thermal noise, die area, and gain error.

Restricting quantizer codes in a delta-sigma modulator cuts PWM-driven transducer noise and inter-symbol interference while preserving mode flexibility.

Wideband signals are split into narrow frequency subbands so parallel noise-shaping ADC branches can raise resolution while limiting jitter and thermal noise.

Parallel higher-bit processing avoids carry propagation delays in second-order delta-sigma modulation, enabling higher speed and wider bandwidth.

Simultaneous sigma-delta sampling of self, mutual, and pen capacitance cuts touch sample time while improving noise rejection on large displays.

Phase conversion, multiplexing, and interleaving let one RF up-converter support 3:1 and 6:1 modes with higher bandwidth and lower chip cost.

Parallel frequency-shifted sigma-delta branches shape quantization noise away from wideband signals, reducing sampling demands.

A delta-sigma predictor adjusts quantization step size to capture small neural signals without saturation from large transients.

A deterministic out-of-band injection signal suppresses delta-sigma modulator idle tones while preserving SNR and dynamic range.

An AC-coupled sigma-delta TOF receiver removes ambient-light DC offset to avoid saturation and preserve distance accuracy.

A shared bias voltage across p-type and n-type transistors cuts sigma-delta ADC power use without sacrificing conversion precision.