Switched-Capacitor Amplifier Topology for High Input Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Switched capacitor amplifiers face challenges in achieving high input impedance, leading to loading issues, gain errors, settling time errors, and signal distortions, which are exacerbated by low impedance and require additional clock signals that increase power consumption and limit operating speed and bandwidth.
Innovation Solution
The implementation of a switched capacitor amplifier with extra capacitors that allow for coarse and fine charging in different phases of a single clock signal, eliminating the need for extra clock signals and utilizing buffers to receive inputs, thereby boosting input impedance without introducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional clock signals are used to improve input impedance, then input impedance is improved, but power consumption increases and operating speed is limited
Solution Approach 1:
The capacitor array is divided into multiple sub-capacitors that can be independently controlled. By selectively connecting subsets of these sub-capacitors to different input signals during different phases, the circuit achieves high input impedance without requiring additional clock signals, thus avoiding increased power consumption while maintaining fast operating speed
Solution Approach 2:
The circuit uses dynamic switching of capacitor connections controlled by a single clock signal. The switching network dynamically reconfigures which capacitors are connected to which inputs during different phases, enabling high input impedance through time-multiplexed operation rather than through static additional signaling
2Reliability
If additional clock signals are used to improve input impedance, then input impedance is improved, but operating speed and bandwidth are limited
Solution Approach 1:
The capacitor array is segmented into multiple sub-capacitors that can be independently switched. This segmentation allows the circuit to process multiple input signals through time-multiplexed sampling using a single clock signal, avoiding the bandwidth limitations that would result from using multiple clock signals and enabling faster operation
Solution Approach 2:
The circuit employs periodic switching of the capacitor connections controlled by a single clock signal. During different phases of the clock cycle, different subsets of capacitors are connected to different inputs, achieving high input impedance through periodic reconfiguration rather than through continuous additional signaling, thus maintaining high operating speed and bandwidth
3Device complexity
If low impedance is used, then circuit complexity is reduced, but loading issues and gain errors occur
Solution Approach 1:
The switched capacitor array acts as an intermediary between the input signals and the main amplifier circuit. By using the capacitor array to sample and hold input voltages, the circuit achieves high input impedance without requiring the main amplifier to have high input impedance, thus avoiding loading issues and gain errors while keeping the overall circuit relatively simple
Solution Approach 2:
The capacitor array automatically performs the function of impedance transformation and signal sampling. The capacitors naturally charge to the input voltage levels during the sampling phase, and this charge is then transferred to the amplifier inputs, providing high input impedance and accurate signal transfer without requiring additional active components or complex circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves high input impedance with reduced power consumption, minimal area usage, and the ability to operate at higher frequencies without extra clock signals, minimizing power consumption and enhancing performance.
Implementation Method 1
a first buffer circuit configured to charge a first plurality of capacitors during a first time period
Implementation Method 2
A switch circuit is configured to, during a second time period, cause a modification of an amount of charge stored on one of the first plurality of capacitors by coupling an input signal directly to the one of first plurality of capacitors
Data Source
AI summary
A high input impedance switched capacitor amplifier is disclosed. The switched capacitor amplifier includes at least a first buffer circuit configured to charge a first plurality of capacitors during a first time period. A switch circuit is configured to, during a second time period, cause a modification of an amount of charge stored on one of the first plurality of capacitors by coupling an input signal directly to the one of first plurality of capacitors. An amplifier circuit is configured to, based on a sampling voltage present on one of the first plurality of capacitors, generate an output signal.