Resolver Signal Processing with Fine Time Quantization

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Solution Overview

Problem

Existing methods for processing analog measured-value signals in resolver systems face limitations in synchronization due to coarse time quantization, which restricts the precision of synchronization control in industrial applications, especially when secondary control loops need to be synchronized with primary loops.

Innovation Solution

The method involves processing the measured-value signal through a delta-sigma modulator followed by a series of integrators and a second digital filter that calculates differences between intermediate data words at specific time intervals, allowing for high-resolution time quantization and precise synchronization without the need for differentiators or reset devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a decimation filter with integrators operated at low clock-pulse frequency is used for analog-digital conversion, then the filter effect is sufficient, but the time quantization is coarse which limits synchronization precision

Engineering Contradiction:
Improvefilter effectVSAvoidtime quantization
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent divides the signal processing into two separate stages: a first digital filter (decimation filter) that performs analog-digital conversion with integrators at low frequency to ensure adequate filtering, and a second digital filter that operates at high frequency to provide precise time quantization. This segmentation allows each filter to optimize for its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediate data-word stream as a mediator between the first and second digital filters. The first filter produces intermediate data words at low frequency, which are then processed by the second filter at high frequency. This intermediate representation enables the system to achieve both adequate filtering and precise time quantization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the measuring duration is set to integral multiples of the decimation clock period, then the system is simple to operate, but the synchronization quality is limited

Engineering Contradiction:
Improvemeasuring duration settingVSAvoidsynchronization quality
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent makes the measuring duration dynamic by allowing it to be independently adjusted in the second digital filter based on the application requirements. The measuring duration is no longer constrained to integral multiples of the decimation period, enabling precise synchronization while maintaining operational simplicity through digital control.

Inventive Principle:
Principle #15Dynamics

3Ease of manufacture

If differentiators and reset devices are used in the decimation filter, then the analog-digital conversion can be implemented, but the device complexity increases

Engineering Contradiction:
Improveanalog-digital conversion implementationVSAvoidfilter structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent replaces the traditional mechanical/differentiator-based approach with a purely digital filtering approach. Instead of using differentiators and reset devices, the system uses two digital filters where the second filter processes the intermediate data to achieve the desired conversion, eliminating complex mechanical components.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10735022B2Method for processing a measured-value signal determined in an analog manner, a resolver system for implementing the method and a method for determining an output current of a converter
Publication Date: 2020.08.04 SEW EURODRIVE GMBH & CO KG
  • US10735022B2 patent drawing
  • US10735022B2 patent drawing
  • US10735022B2 patent drawing

AI summary

In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.