Diode-Connected Delay Cell for Large Delays With Lower Power

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing delay circuits requiring large delays, such as 100 ns, consume substantial power and semiconductor die space due to the need for a large number of inverters.

Innovation Solution

A delay cell design incorporating diode-connected transistors in serial stacks of PMOS and NMOS transistors to introduce resistance and delay transitions, reducing the number of transistors needed for significant delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a serial chain of inverters is used to generate large delay (e.g., 100 ns), then the delay capability is improved, but the power consumption and semiconductor die space increase substantially

Engineering Contradiction:

Improvedelay capabilityVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The delay circuit is segmented into multiple delay cells, each contributing a portion of the total delay. Each delay cell contains a specific configuration of transistors (PMOS and NMOS in serial stacks with diode-connected transistors) that generates a controlled delay increment. By cascading multiple such cells, the total delay of 100 ns or more is achieved while each individual cell consumes minimal power, thus resolving the contradiction between large delay capability and power consumption.

Inventive Principle:

Principle #1Segmentation

2Loss of time

If a serial chain of inverters is used to generate large delay (e.g., 100 ns), then the delay capability is improved, but the semiconductor die space increases substantially

Engineering Contradiction:

Improvedelay capabilityVSAvoidsemiconductor die space

Core Design Contradiction:

Loss of timeVSArea of stationary object

Solution Approach 1:

Multiple transistors are merged into compact serial stack configurations within each delay cell. The PMOS and NMOS transistors are stacked in series with diode-connected transistors, allowing efficient space utilization. This merging approach achieves the required delay function in a compact footprint, enabling 100 ns delay generation without substantial die space increase.

Inventive Principle:

Principle #5Merging (Combining)

3Loss of time

If the number of inverters is increased to provide larger delay, then the delay capability is improved, but the device complexity increases

Engineering Contradiction:

Improvedelay capabilityVSAvoidnumber of transistors

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The delay cell employs dynamic transistor switching through the serial stack configuration. The diode-connected transistors dynamically control the switching behavior of the PMOS and NMOS transistors, enabling each cell to generate substantial delay with a limited number of transistors. This dynamic operation allows achieving 100 ns delay without linearly increasing the transistor count, thus reducing device complexity compared to static inverter chains.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250260397A1Efficient cell for large delay generation

Publication Date: 2025.08.14 QUALCOMM INC

AI summary

A delay cell includes two serial stacks of transistors. Each serial stack includes a PMOS transistor having a source coupled to a power supply node for a power supply voltage and includes an NMOS transistor having a source coupled to ground. In each serial stack, at least one diode-connected transistor is coupled between a drain of the PMOS transistor and a drain of the NMOS transistor.