Parallel Second-Order Delta-Sigma Modulator for Carry Delay Limits
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Solution Overview
Problem
Current delta-sigma modulation technologies face challenges in achieving high-speed operation for second-order or higher modulation due to carry propagation delays, limiting their ability to handle wide bandwidth signals effectively and maintain a good signal-to-noise ratio, especially in future wireless communication systems.
Innovation Solution
A second-order delta-sigma modulator design that incorporates a parallel higher-bit processing part with addition and determination processing sections, selectors, and a sign determination unit, which receives carry inputs and state inputs to produce quantized outputs, thereby avoiding carry propagation delays and enabling high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If second-order or higher delta-sigma modulation is used to improve signal-to-noise ratio and bandwidth handling, then modulation performance is improved, but operating speed decreases due to carry propagation delays
Solution Approach 1:
The higher-bit processing part is divided into multiple parallel processing sections (first through M-th sections) that operate simultaneously. Each section processes a portion of the carry inputs independently, eliminating the sequential carry propagation delay that would otherwise limit operating speed in second-order delta-sigma modulation.
Solution Approach 2:
The patent transitions from sequential single-channel processing to parallel multi-channel processing by introducing M parallel processing sections. This dimensional expansion allows multiple carry processing operations to occur simultaneously, resolving the speed limitation while maintaining the noise shaping benefits of second-order modulation.
2Adaptability or versatility
If second-order or higher delta-sigma modulation is used to support wide bandwidth signals, then bandwidth capability is improved, but operating speed decreases due to carry propagation delays
Solution Approach 1:
The higher-bit processing part is divided into multiple parallel processing sections (first through M-th sections) that operate simultaneously. Each section processes a portion of the carry inputs independently, eliminating the sequential carry propagation delay that would otherwise limit operating speed in second-order delta-sigma modulation.
Solution Approach 2:
The patent transitions from sequential single-channel processing to parallel multi-channel processing by introducing M parallel processing sections. This dimensional expansion allows multiple carry processing operations to occur simultaneously, resolving the speed limitation while maintaining the noise shaping benefits of second-order modulation.
3Speed
If pipeline processing is used to eliminate carry propagation delay in first-order modulation, then operating speed is improved, but noise suppression function in vicinity of desired signal remains low
Solution Approach 1:
The patent changes the modulation order from first-order to second-order or higher, fundamentally altering the noise transfer function characteristics. This parameter change enables superior noise suppression in the signal band while the parallel processing structure maintains high operating speed, resolving the trade-off between noise performance and speed.
Data Source
AI summary
A second-order ΔΣ modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.