Data-Weighted DAC Element Rotation for Mismatch and Idle Tone Control
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Solution Overview
Problem
Multibit sigma-delta digital-to-analog converters (DACs) face performance degradation due to element mismatch, leading to harmonic distortions and increased noise, which existing dynamic element matching techniques partially address but introduce idle tones and high power consumption.
Innovation Solution
The proposed solution involves a data-weighted element rotation scheme that splits input signals into time-interleaved streams, using element rotation selection logic to direct these streams based on a data-weighted sigma-delta modulator's decisions, reducing sample rate and disabling unused paths to minimize mismatch errors and idle tones, while ensuring equal usage of elements to reduce noise transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic element matching techniques are used to correct element mismatch, then signal-to-noise ratio and total-harmonic-distortion performance are improved, but idle tones are introduced and power consumption increases
Solution Approach 1:
The input data stream is segmented into multiple parallel sub-streams that are processed through separate ERS logic paths. This segmentation allows the system to distribute the mismatch correction task across multiple paths, reducing the likelihood of generating idle tones while maintaining effective mismatch shaping.
Solution Approach 2:
The element rotation selection logic implements periodic switching between different element configurations based on the segmented data streams. This periodic action distributes the element usage over time, preventing the concentration of errors that lead to idle tones while maintaining continuous mismatch correction.
2Measurement precision
If dynamic element matching techniques are used to correct element mismatch, then signal-to-noise ratio and total-harmonic-distortion performance are improved, but power consumption increases
Solution Approach 1:
The data stream is divided into multiple segmented streams that are processed in parallel through separate ERS logic units. This segmentation enables power management by allowing the system to activate only the necessary number of ERS logic paths based on the current data requirements, reducing overall power consumption while maintaining mismatch correction effectiveness.
Solution Approach 2:
The system dynamically disables unused data paths and recovers power by putting idle ERS logic units into low-power states. This approach maintains mismatch correction performance by keeping only the necessary number of paths active, thereby reducing power consumption without sacrificing signal-to-noise ratio.
3Measurement precision
If element rotation selection logic processes all time interleaved data streams, then mismatch correction is maximized, but hardware complexity increases
Solution Approach 1:
The data stream is segmented into multiple parallel streams that can be processed independently through separate ERS logic units. This segmentation allows the system to implement mismatch correction with modular hardware blocks, reducing overall hardware complexity by distributing the correction task across simpler, independent units rather than requiring a single complex processing unit.
Solution Approach 2:
Multiple ERS logic units are designed with identical, universal functionality to process different segmented data streams. This universality reduces hardware complexity by using replicated simple blocks rather than a single complex unit, as each block performs the same mismatch correction function on its assigned data stream.
Data Source
AI summary
Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.