Digital Class D Driver Feedback ADC for Lower-Power Error Correction
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Solution Overview
Problem
Conventional class D amplifiers face inefficiencies in power dissipation, leading to heat generation and reduced battery life in portable systems, due to their continuous output current supply.
Innovation Solution
A digital class D driver architecture incorporating a feedback analog-to-digital converter with a low power consumption and one clock cycle delay, featuring a digital modulator, power stage, and an analog feedback loop with a loop filter and quantizers, which separates error content from signal content to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional class D amplifiers supply continuous output current, then the output stage can maintain continuous signal transmission, but power dissipation becomes large and heat generation increases
Solution Approach 1:
The patent applies periodic switching action in the output stage, where transistors switch between positive and negative power supplies in pulsed manner rather than continuous conduction. This creates voltage pulses that drive the load while minimizing simultaneous current flow through both transistors, thereby reducing power dissipation and heat generation in the output stage.
Solution Approach 2:
The patent implements dynamic switching control where the output transistors operate in a highly dynamic state, transitioning rapidly between on and off states. This dynamic operation ensures that transistors have zero current when not switching and low voltage when conducting, optimizing the trade-off between signal transmission and power efficiency at each moment.
2Measurement precision
If a feedback ADC with fast conversion is used, then the feedback loop can achieve high precision, but the ADC power consumption increases
Solution Approach 1:
The patent segments the feedback signal processing into two distinct paths: a high-precision path for DC and low-frequency components using a precision ADC, and a high-speed path for AC components using a faster ADC. This segmentation allows each ADC to be optimized for its specific function, with the precision ADC consuming less power for low-bandwidth precision tasks while the fast ADC handles high-frequency content.
Solution Approach 2:
The patent applies different quality levels of conversion to different frequency components of the feedback signal. Low-frequency components requiring high precision are processed by a precision ADC, while high-frequency components are processed by a faster ADC with acceptable but lower precision. This local differentiation optimizes overall power consumption while maintaining necessary precision where required.
3Reliability
If the feedback loop processes the entire output signal, then complete signal accuracy is maintained, but power consumption increases due to processing all signal content
Solution Approach 1:
The patent segments the feedback signal into error content and signal content components. The error content, representing deviations from the desired output, is processed through the feedback loop to correct distortions and maintain accuracy. The signal content is handled separately through feedforward paths. This segmentation allows the feedback loop to process only the essential error corrections rather than the entire signal, significantly reducing power consumption while maintaining signal accuracy.
Solution Approach 2:
The patent extracts and removes the signal content from the feedback loop processing path, leaving only the error content to be processed. By taking out the redundant signal content that doesn't require feedback correction, the system reduces the computational burden and power consumption of the feedback loop while preserving the necessary error correction functionality for signal accuracy.
Data Source
AI summary
Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.