In-Loop Buffer ADC Circuit for Low-Power High-Fidelity Audio

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Solution Overview

Problem

Wearable audio devices such as earbuds and headphones face challenges in providing high-fidelity audio reproduction while operating in a power-efficient manner due to limited battery capacity and the need for efficient power management.

Innovation Solution

The implementation of an analog-to-digital converter circuit with a specific capacitor configuration and amplifier architecture that includes in-loop buffers, allowing for dynamic switching between high-output resistance and zero-output resistance modes to optimize power efficiency and audio performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional ADC circuits are used in wearable audio devices, then audio processing functionality is provided, but power consumption is high and battery life is limited

Engineering Contradiction:
Improvepower consumptionVSAvoidbattery life
Core Design Contradiction:
Use of energy by moving objectVSDuration of action of moving object

Solution Approach 1:

The patent applies parameter changes by dynamically switching the output resistance of the ADC between high and zero states based on operational requirements. This allows the circuit to consume power only when needed (high output resistance mode for signal transmission) and enter a low-power state when continuous signal transmission is not required (zero output resistance mode), thereby reducing overall power consumption and extending battery life in wearable audio devices.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If high-output resistance mode is used for audio signal transmission, then audio fidelity is improved, but power consumption increases

Engineering Contradiction:
Improveaudio fidelityVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamics by making the output resistance of the ADC variable rather than fixed. The circuit dynamically transitions between high-output resistance mode (for high-fidelity audio signal transmission) and zero-output resistance mode (for power saving). This dynamic adaptation allows the system to optimize the trade-off between audio fidelity and power consumption based on real-time operational needs, such as whether audio data is being actively transmitted to the speaker.

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If mode switching is implemented to optimize power efficiency, then power consumption is reduced, but audio artifacts may occur during transitions

Engineering Contradiction:
Improvepower consumptionVSAvoidaudio artifacts
Core Design Contradiction:
Use of energy by moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent employs feedback mechanisms to monitor and control the transitions between high-output resistance and zero-output resistance modes. By using feedback from the audio signal path and power management system, the circuit can execute mode switches at optimal moments (e.g., during silence periods or low-signal intervals) and maintain stability during transitions, thereby minimizing the generation of audio artifacts while still achieving power consumption reduction through mode switching.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250219649A1Analog-to-digital converter with in-loop buffer
Publication Date: 2025.07.03 SKYWORKS SOLUTIONS INC
  • US20250219649A1 patent drawing
  • US20250219649A1 patent drawing
  • US20250219649A1 patent drawing

AI summary

A circuit of an analog-to-digital converter comprises a first transistor, a first capacitor coupled to a gate of the transistor, a second capacitor coupled to a source of the transistor, the second capacitor having a higher capacitance relative to the first capacitor, and a first amplifier, an input of the first amplifier being coupled to the second capacitor.