DAC Element Ordering for Higher SNDR in Sigma-Delta ADCs
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Solution Overview
Problem
Sigma-Delta Analog-to-Digital Converters (ADCs) face significant nonlinearity due to feedback through Digital-to-Analog Converters (DACs), limiting system performance and requiring higher oversampling ratios, increased power consumption, or area expansion to mitigate distortion.
Innovation Solution
Optimizing the linearity of a DAC in a Sigma-Delta ADC by selecting the order of DAC unary current sources to minimize cumulative offset currents, achieved through a series of analog-to-digital conversions and Fast Fourier Transform analysis to determine an optimized element ordering stored in a lookup table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If feedback is introduced through DAC to convert digital output back to analog form, then the Sigma-Delta ADC can perform analog-to-digital conversion, but significant nonlinearity is introduced that limits system performance
Solution Approach 1:
The patent applies preliminary action by measuring and characterizing DAC element errors before the actual conversion process. During a calibration phase, each DAC element's error is measured and stored. During normal operation, the pre-measured error data is used to select optimal element combinations that minimize nonlinearity, thereby resolving the contradiction between achieving accurate conversion and avoiding nonlinearity-induced performance degradation
Solution Approach 2:
The patent changes the operational parameters of the DAC by dynamically selecting different combinations of DAC elements based on the desired output level. Instead of using a fixed set of elements, the system varies which elements are activated and applies pre-measured error compensation values, thereby reducing nonlinearity while maintaining conversion accuracy
2Manufacturing precision
If redundant unary DAC elements are added to reduce switching error and optimize calibration, then second order distortion is reduced, but device complexity and area increase
Solution Approach 1:
The patent applies partial action by using only the necessary number of DAC elements required to achieve the desired precision level. Instead of implementing all possible redundant elements, the system measures errors for available elements and selects the optimal subset that provides sufficient distortion reduction without unnecessary area overhead or complexity
Solution Approach 2:
The patent changes the operational configuration of the DAC elements by dynamically selecting which elements to use based on error measurements. This allows the system to achieve low distortion using a optimized subset of elements rather than requiring all elements to be physically present and active, thereby reducing device complexity while maintaining precision
3Measurement precision
If higher oversampling ratios are used to mitigate distortion, then system performance improves, but power consumption and processing requirements increase
Solution Approach 1:
The patent converts the harmful effect of DAC nonlinearity into a beneficial outcome by measuring and characterizing the errors, then using this knowledge to selectively compensate for nonlinearity. This approach eliminates the need for higher oversampling ratios that would otherwise be required to achieve the same performance, thereby reducing power consumption while maintaining or improving system performance
Solution Approach 2:
The patent changes the approach from increasing oversampling ratio to changing the DAC element selection and error compensation parameters. By optimizing which elements are used and how their errors are compensated, the system achieves improved performance without the power consumption penalty associated with higher oversampling ratios
4Manufacturing precision
If DAC element ordering is optimized to minimize cumulative offset currents, then linearity improves and SNDR increases, but additional measurement and calibration time is required
Solution Approach 1:
The patent applies preliminary action by performing error measurements and element optimizations during an initial calibration phase before normal operation begins. The results of this preliminary work are stored and reused during actual conversion operations, thereby achieving improved linearity without incurring time penalties during the critical measurement and conversion phases
Solution Approach 2:
The patent creates a copy of the error characteristics for each DAC element during calibration and stores this data for reuse. Instead of repeatedly measuring errors during normal operation, the system uses the pre-created error data copies to quickly determine optimal element selections, thereby reducing calibration time while maintaining linearity improvements
Data Source
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AI summary
A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.