Multibit DAC Linearization for Low-Delay Sigma-Delta ADCs
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Solution Overview
Problem
Existing sigma-delta analog-to-digital converters (ADCs) face challenges with non-linearities due to mismatches in multibit digital-to-analog converter (DAC) elements, which can lead to reduced accuracy and increased delay in feedback loops, particularly in high-speed applications.
Innovation Solution
A sigma-delta modulator design that includes a multibit quantizer with a mapping engine for sorting, mapping, and switching operations, decoupled from the main feedback loop, allowing for linearization of DAC elements without contributing to total loop delay, and utilizing an excess loop delay DAC to manage feedback signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing linearization techniques are applied to correct DAC mismatches, then manufacturing precision of DAC elements is improved, but delay in the feedback loop increases
Solution Approach 1:
The patent segments the feedback loop into two independent paths: a main feedback path for signal conversion and a separate linearization path for DAC mismatch correction. The linearization path includes a linearization DAC and mapping engine that operate independently from the main feedback loop, allowing mismatch correction without adding delay to the critical feedback path.
Solution Approach 2:
The patent introduces a linearization DAC as an intermediary component that generates correction signals separately. This intermediary device allows the system to correct DAC mismatches through a dedicated linearization path that does not interfere with the timing-critical main feedback loop, thereby improving manufacturing precision without increasing feedback delay.
2Productivity
If a multibit DAC is used in the feedback loop, then productivity of the ADC is improved, but manufacturing precision deteriorates due to element mismatches
Solution Approach 1:
The patent divides the DAC functionality into two separate components: a main multibit DAC for high-speed signal conversion and a linearization DAC for precision mismatch correction. This segmentation allows the main DAC to operate at high speed without being constrained by manufacturing tolerances, while the linearization DAC handles the precision correction independently.
Solution Approach 2:
The patent implements a feedback mechanism where a mismatch sensor continuously monitors the main DAC element mismatches and feeds this information to a mapping engine. The mapping engine then generates corrected reference signals for the linearization DAC, creating a closed-loop system that automatically compensates for manufacturing variations while maintaining high conversion speed.
3Manufacturing precision
If linearization techniques are implemented within the feedback loop, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the linearization functionality from the main feedback loop and places it in a separate, parallel path. By taking out the mapping engine and linearization DAC from the critical feedback path, the patent reduces the complexity of the feedback loop itself while still achieving DAC linearization through the independent correction path.
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AI summary
The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.