CT ADC Calibration with DAC Mismatch Error Correction
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Solution Overview
Problem
Continuous-time analog-to-digital converters (CT ADCs) face challenges in accurately estimating analog transfer functions due to mismatch in the injection DAC, leading to poor noise spectral density (NSD) at the ADC output, especially when dealing with input signals.
Innovation Solution
The implementation of a CT ADC system that includes a delay circuit, a sub-ADC circuit, a sub-DAC circuit, an error estimation circuit, and an error correction circuit, which generates a residue signal and a digital error-correction signal to improve the accuracy of transfer function estimation by combining these signals to produce the ADC output, thereby mitigating the effects of DAC mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a pseudo random bit sequence is injected using a DAC to estimate the transfer function, then the transfer function can be measured, but mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output
Solution Approach 1:
The patent implements a feedback mechanism where the ADC output is fed back through a digital-to-analog converter and combined with the delayed input signal. This feedback path allows for continuous monitoring and correction of transfer function estimation errors, enabling the system to compensate for DAC mismatch and improve both measurement precision and NSD performance simultaneously
Solution Approach 2:
The patent introduces a delay circuit as an intermediary element that creates a delayed version of the input signal. This delayed signal serves as a reference that can be combined with the feedback signal to isolate and measure the transfer function independently of the original input, thereby eliminating the harmful effect of DAC mismatch on measurement accuracy
2Productivity
If the ADC operates with high speed and high resolution requirements, then conversion performance is improved, but the complexity of designing and calibrating the ADC increases
Solution Approach 1:
The patent divides the ADC into multiple functional blocks including a delay circuit, feedback path, digital-to-analog converter, and signal combiner. This segmentation allows each component to be optimized independently for high-speed operation while the overall system complexity is managed through modular design, enabling high conversion performance without proportionally increasing design difficulty
Data Source
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AI summary
CT ADCs based on continuous-time residue generation systems require accurate estimation of analog transfer functions. This is done by using a pseudo random bit sequence, injected using a DAC, that traverses the transfer function to be measured. Mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output. Techniques are described to improve the accuracy of the transfer function estimate despite DAC mismatch and despite the presence of an input signal.