Delta-Sigma Modulator Truncation Compensation for Lower DAC Complexity
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Solution Overview
Problem
Conventional delta-sigma modulators with multi-bit quantizers face mismatch errors due to DAC cell mismatches, leading to non-linearity in analog outputs, and existing dynamic element matching strategies increase hardware complexity exponentially with bit number.
Innovation Solution
A delta-sigma modulator with truncation error compensation, comprising a combining circuit, loop filter circuit, quantizer circuit, truncator circuit, DAC circuit, and compensation circuit, which generates a truncation error compensation signal to reduce bit number and mitigate truncation errors, thereby simplifying hardware and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-level feedback DAC is used in a delta-sigma modulator, then the noise-shaping function is improved, but the hardware complexity grows exponentially as the bit number increases
Solution Approach 1:
The patent segments the feedback DAC into multiple sub-DACs, each handling a specific bit range. This segmentation allows the system to achieve multi-bit noise-shaping functionality while keeping each individual sub-DAC simple, thereby avoiding exponential hardware complexity growth.
Solution Approach 2:
The patent introduces a time dimension by using sequential switching between different sub-DACs. Instead of parallel multi-bit DACs that would require exponential complexity, the system achieves equivalent functionality through time-multiplexed operation of simpler sub-DACs.
2Manufacturing precision
If the bit number of the feedback DAC is increased, then the linearity is improved, but the hardware complexity increases
Solution Approach 1:
The feedback DAC is divided into multiple sub-DACs with different bit resolutions. This segmentation allows the system to achieve high overall linearity by combining multiple lower-resolution sub-DACs, avoiding the need for a single high-resolution DAC that would require exponential hardware resources.
Solution Approach 2:
The patent changes the bit resolution parameter across different sub-DACs, with each sub-DAC optimized for specific bit ranges. This parameter variation allows efficient resource allocation where higher resolution is only applied where needed, maintaining linearity while controlling hardware complexity.
3Device complexity
If truncation is applied to reduce bit number, then hardware complexity is reduced, but truncation errors are introduced
Solution Approach 1:
The patent performs preliminary dithering before truncation by adding a random signal to the digital output. This preliminary action randomizes the truncation error, preventing systematic distortion and allowing the error to be treated as noise rather than a deterministic distortion component.
Solution Approach 2:
The patent converts the harmful truncation error into a beneficial form by using dithering. The truncation error, which would normally cause distortion, is transformed into randomized noise through dithering, which can be filtered more effectively and does not create spurious tones or distortion products.
Data Source
AI summary
A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.