Sigma-Delta Integrator Double Sampling for Low-Noise ADCs
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Solution Overview
Problem
Conventional Sigma-Delta modulators face challenges in improving signal-to-noise ratio (SNR) while maintaining low power consumption and overall area, particularly limited by input referred thermal noise in low power designs.
Innovation Solution
The integrator circuit for a Sigma-Delta modulator incorporates a differential amplifier with sampling and reference capacitors, controlled by non-overlapping clock signals and switching signals, employing a double sampling scheme to connect capacitors and reference switches based on thermometrically coded quantizer signals, which improves SNR without increasing power consumption or area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling capacitance is increased to reduce input referred thermal noise, then the signal-to-noise ratio is improved, but the power consumption increases
Solution Approach 1:
The patent implements double sampling where capacitors are connected to different nodes during different phases (first sampling phase connects to common terminal, second sampling phase connects to differential input terminal). This periodic switching allows noise cancellation without requiring continuously large capacitance, thereby improving SNR while controlling power consumption through phase-based operation rather than continuous high-capacitance state
Solution Approach 2:
The patent changes the connection state parameter of the sampling capacitors between two distinct phases: during the first sampling phase, capacitors are connected to a common terminal; during the second sampling phase, they are connected to differential input terminals. This parameter switching enables thermal noise cancellation through differential operation, achieving improved SNR without the need for continuously increased capacitance values that would proportionally increase power consumption
2Measurement precision
If the sampling capacitance is increased to reduce input referred thermal noise, then the signal-to-noise ratio is improved, but the overall area increases
Solution Approach 1:
The patent uses periodic switching between two sampling phases with a fixed capacitance value. During the first phase, capacitors sample from a common terminal; during the second phase, they sample from differential input terminals. This time-division approach allows the same physical capacitors to serve multiple functions, achieving noise cancellation without requiring additional capacitor area, thus improving SNR while maintaining compact overall area
Solution Approach 2:
The sampling capacitors perform multiple functions: they store signal charge during the first sampling phase, then participate in differential noise cancellation during the second sampling phase. This multi-functionality allows a single set of capacitors to achieve both signal storage and noise reduction, eliminating the need for separate capacitor sets and thereby improving SNR without proportionally increasing the overall circuit area
3Device complexity
If conventional single sampling is used, then the circuit is simple, but the signal-to-noise ratio is limited by thermal noise
Solution Approach 1:
The patent introduces a second sampling phase that periodically switches the capacitor connections to differential input terminals, creating a time-based differential operation. This periodic action introduces noise cancellation capability without fundamentally redesigning the entire circuit architecture, thus improving SNR while maintaining relatively simple circuit complexity through phase-based operation
Solution Approach 2:
The patent performs a preliminary sampling action during the first sampling phase where capacitors are connected to a common terminal, establishing a reference state before the second sampling phase uses differential input terminals. This preliminary action prepares the capacitor voltages for subsequent differential comparison, enabling thermal noise cancellation through the difference between the two sampling states, thereby improving SNR with minimal additional circuit complexity
Data Source
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AI summary
The disclosure relates to an integrator circuit (300) for a Sigma-Delta, ΣΔ, modulator, the integrator circuit (300) comprising an integrator module (310) comprising a differential amplifier (301), a sampling module (320) comprising sampling capacitors (CS1p, CS2p, CS1n, CS2n) and a reference module (330) comprising first and second pluralities of reference capacitors (3311-x, 3321-x) connected between respective first and second lines (308, 309) and first and second pluralities of reference switches (3311-x, 3321-x) for connecting each of the reference capacitors (3311-x, 3321-x) to either a first reference terminal (324) or a second reference terminal (325). In operation, the reference switches (3311-x, 3321-x) are switched according to a thermometrically coded quantizer signal.