Shared-Op-Amp Delta-Sigma ADC Integrator for Low-Power Resolution
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Solution Overview
Problem
Conventional delta-sigma type analog-to-digital converters (ADCs) face challenges in achieving high-resolution performance while maintaining low power consumption, high signal-to-noise ratio (SNR), and low total harmonic distortion (THD), primarily due to the operating characteristics of operational amplifiers (op-amps) used in these systems.
Innovation Solution
The implementation of a delta-sigma type ADC with an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier, allowing for simultaneous sampling and integration, which reduces power consumption and enhances noise shaping capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the current is increased to achieve high-resolution audio in conventional ADCs, then the resolution is improved, but the power consumption increases
Solution Approach 1:
The patent merges the sampling and integration functions into a single circuit stage using two switched-capacitor circuits that share a single operational amplifier. This consolidation eliminates the need for separate sampling and integration stages, reducing the total current requirement while maintaining high-resolution performance. The shared op-amp configuration allows both functions to operate simultaneously with reduced power consumption.
Solution Approach 2:
The patent employs periodic switching of the capacitor circuits controlled by clock signals to alternately perform sampling and integration operations. This periodic action enables the circuit to achieve high-resolution conversion through time-multiplexed operation, maintaining precision without requiring continuously high current levels that would increase power consumption.
2Measurement precision
If conventional ADC architectures are used to achieve high-resolution performance, then the resolution is improved, but the signal-to-noise ratio and total harmonic distortion deteriorate
Solution Approach 1:
By combining sampling and integration into a single stage with shared capacitors and operational amplifier, the patent reduces the number of signal transfer points and potential noise sources. This merged architecture maintains better signal integrity and reduces accumulated noise, improving the signal-to-noise ratio while achieving high resolution.
Solution Approach 2:
The patent uses two switched-capacitor circuits that are substantially identical in structure, allowing one circuit to perform sampling while the other performs integration simultaneously. This symmetric copying approach ensures matched performance characteristics and reduces distortion, maintaining high signal-to-noise ratio.
3Measurement precision
If conventional ADC architectures are used to achieve high-resolution performance, then the resolution is improved, but the total harmonic distortion increases
Solution Approach 1:
The merged sampling and integration stage reduces the number of active components and signal paths, minimizing non-linearities and harmonic distortion generation. The single operational amplifier configuration with shared capacitors provides more consistent gain and phase characteristics, reducing total harmonic distortion while maintaining high resolution.
Solution Approach 2:
The use of two matched switched-capacitor circuits performing sampling and integration simultaneously ensures symmetric signal processing paths. This copying approach balances the circuit operation and reduces even-order harmonic distortion, improving overall signal fidelity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the ADC to achieve high-resolution performance without increasing current consumption, maintaining low power consumption and improving signal-to-noise ratio and total harmonic distortion, while effectively reducing quantization noise.
Implementation Method 1
an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier
Data Source
AI summary
Various embodiments of the present technology may comprise methods and apparatus for an analog-to-digital converter. Methods and apparatus for an analog-to-digital converter (ADC) may be configured as a delta-sigma type ADC and include an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier. The switched-capacitor circuits receive various control signals such that one SC circuit performs sampling while the other SC circuit simultaneously performs integration.