Time-Interleaved DAC Spur Correction in Delta-Sigma ADCs

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Solution Overview

Problem

Time-interleaved digital-to-analog converters (DACs) used in delta-sigma analog-to-digital converters (ADCs) face challenges due to increased complexity, requiring precise matching of channels and sub-ADCs, which leads to interleaving spurs caused by clock duty errors, degrading signal-to-noise (SNR) performance.

Innovation Solution

A circuit and method involving a dither tone generator and digital signal processing are used to measure and correct interleaving spurs in time-interleaved DACs. The dither tone is injected into the ADC, and the digital signal processing circuit processes the output to generate a measurement result, which is then used by a control circuit to adjust the spur correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If time-interleaved DACs are used to increase sampling rate, then productivity is improved, but device complexity increases and interleaving spurs are generated

Engineering Contradiction:
ImproveDAC sampling rateVSAvoidcomplexity of multiple identical channels
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the timing parameters of the dither tone injection relative to the clock phases to selectively excite and measure interleaving spurs. By adjusting the injection timing, the system can characterize spur behavior under different phase conditions without requiring hardware changes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

A dither tone is introduced as an intermediary signal to indirectly measure the interleaving spur characteristics. The dither tone acts as a probe that interacts with the DAC system, allowing the measurement of spur behavior without directly observing the problematic clock duty cycle effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If time-interleaved DACs are used to increase sampling rate, then productivity is improved, but measurement precision deteriorates due to interleaving spurs

Engineering Contradiction:
ImproveDAC sampling rateVSAvoidSNR performance
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent converts the harmful interleaving spurs into a useful measurement tool. By injecting a dither tone and measuring the resulting spur responses, the system characterizes the spur behavior and uses this information for correction, turning the previously harmful effect into a diagnostic and correction mechanism that improves overall measurement precision.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The system implements a feedback loop where the measured interleaving spur characteristics are used to adjust correction parameters. The digital signal processing circuit analyzes the dither tone output and feeds this information back to optimize the spur correction, continuously improving measurement precision.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If clock duty cycle is not 50% in DDR DAC, then ease of operation is improved, but object-generated harmful factors increase due to time-dependent current width

Engineering Contradiction:
Improveflexibility in clock duty cycleVSAvoidinterleaving spur and IL image
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The system takes preliminary action by characterizing the interleaving spur behavior through dither tone injection before normal operation. The measured spur characteristics are stored and used to pre-correct the output, counteracting the harmful effects of non-50% duty cycle clocks before they degrade the signal quality.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent performs preliminary measurement and correction setup using dither tone injection. By characterizing the spur behavior in advance through controlled dither tone testing, the system prepares correction parameters that will compensate for the clock duty cycle effects during actual operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250183909A1Circuit and method for measuring and correcting interleaving spur of at least one time-interleaved digital-to-analog converter in delta-sigma analog-to-digital converter
Publication Date: 2025.06.05 MEDIATEK INC
  • US20250183909A1 patent drawing
  • US20250183909A1 patent drawing
  • US20250183909A1 patent drawing

AI summary

A measuring circuit measures an interleaving (IL) spur of at least one time-interleaved digital-to-analog converter (DAC) included in a delta-sigma (DS) analog-to-digital converter (ADC). The measuring circuit includes a dither tone generator circuit and a digital signal processing circuit. The dither tone generator circuit generates a dither tone with a pre-defined tone frequency, and injects the dither tone to the DS ADC. The digital signal processing circuit processes a digital output of the DS ADC with the dither tone injected, to generate a measurement result of the IL spur that is induced by the at least one time-interleaved DAC due to the injected dither tone.