Sigma-Delta ADC Excess Loop Delay Compensation With Feedforward Capacitors

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Solution Overview

Problem

Sigma-delta ADCs face performance degradation and instability due to parasitic capacitance, which causes incomplete settling of excess loop delay feedback information and introduces parasitic poles in the loop filter path, especially in high-speed applications.

Innovation Solution

Incorporating feedforward capacitors and transconductance cells with compensating zeros in the transfer function to mitigate the effects of parasitic capacitance, improving the settling speed of DAC output and stabilizing the feedback loop.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an excess loop delay (ELD) digital-to-analog converter (DAC) is used to reduce the impact of ELD, then ADC performance is improved, but parasitic capacitance causes incomplete settling of ELD feedback information and degrades performance

Engineering Contradiction:

ImproveADC performanceVSAvoidsettling completeness

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

A feedforward capacitor is introduced as an intermediary element connected in parallel with the ELD DAC. This capacitor acts as a mediator that provides an alternative current path during the transition period, enabling the summing node to reach its final value more quickly and compensating for the incomplete settling caused by parasitic capacitance.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the electrical parameters of the feedback loop by adding a capacitor with specific capacitance value. This changes the time constant and frequency response of the loop, allowing the system to achieve complete settling within the available time budget despite the presence of parasitic capacitance in the ELD DAC path.

Inventive Principle:

Principle #35Parameter changes

2Stability of the object's composition

If an ELD DAC is used to compensate for excess loop delay, then loop stability is improved, but parasitic capacitance introduces parasitic poles in the loop filter path that cause instability

Engineering Contradiction:

Improveloop stabilityVSAvoidparasitic poles

Core Design Contradiction:

Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The feedforward capacitor, which initially appears to simply speed up settling, actually serves the dual function of compensating for the harmful parasitic poles introduced by the ELD DAC's parasitic capacitance. By strategically placing this capacitor, the system converts the settling speed improvement into a stability compensation mechanism that counteracts the phase shift caused by parasitic elements.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11463101B2Techniques for high-speed excess loop delay compensation in sigma-delta analog-to-digital converters

Publication Date: 2022.10.04 NXP BV

AI summary

The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.