Asynchronous Full-Adder Capacitive Gates for Low-Voltage Operation
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Solution Overview
Problem
Existing asynchronous logic circuits face challenges in low voltage conditions, particularly when implementing full-adders with traditional transistor stacks, which are inefficient and difficult to use below 1V.
Innovation Solution
The implementation of asynchronous full-adders using majority and minority gates with capacitive input circuits, including linear or nonlinear dielectric capacitors, reduces the transistor stack and allows operation at lower power supply levels, achieving area reduction and higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional transistor stacks are used to implement full-adders in asynchronous logic, then the circuit can operate at higher voltages with simpler logic gates, but the transistor stack height increases making it difficult to operate in low voltage conditions (1V or less)
Solution Approach 1:
The patent replaces traditional mechanical transistor switching with a capacitive voltage division system. Capacitors are used to store and distribute voltage levels, substituting the mechanical action of transistor gates with electrical field-based voltage storage and release, enabling low-voltage operation without increasing transistor stack height
Solution Approach 2:
The invention changes the voltage parameter distribution across the circuit by using capacitive dividers to create intermediate voltage levels (e.g., Vdd/2, Vdd/4) from a single low-voltage supply. This allows the full-adder to operate correctly at low voltages by dynamically adjusting voltage levels at different circuit nodes rather than requiring high supply voltage
2Productivity
If traditional asynchronous logic circuits are used with stacks of transistors, then the logic can be implemented with standard gates, but the area occupied by the circuit increases and throughput decreases
Solution Approach 1:
The patent merges multiple transistor functions into shared capacitive structures. The capacitive input circuits serve as both voltage storage elements and logic gate inputs, eliminating the need for separate gating structures. This consolidation reduces the total number of components and their occupied area while maintaining full-adder functionality
Solution Approach 2:
The invention transitions from planar transistor stacking to a more three-dimensional capacitive structure where voltage levels are stored and manipulated in the electrical field domain rather than through sequential transistor layers. This dimensional shift allows for more compact area utilization while achieving the required logic depth for full-adder operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables asynchronous circuits to operate efficiently at low voltages, reducing area by up to 3× and increasing throughput by 2× compared to traditional circuits, while also allowing integration into synchronous circuits.
Implementation Method 1
capacitive input circuits, including linear or nonlinear dielectric capacitors
Implementation Method 2
linear or nonlinear dielectric capacitors
Data Source
AI summary
Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.