Capacitive C-Element Consensus Circuit for Low-Voltage Asynchronous Logic
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Solution Overview
Problem
Existing asynchronous logic circuits face challenges in operating efficiently at low voltage conditions and require significant stacks of transistors between power supply and ground, leading to area inefficiencies and reduced throughput.
Innovation Solution
The development of asynchronous circuits using threshold gates and capacitive input circuits with linear or nonlinear dielectric materials, which reduce the stack of devices and enable operation at lower power supply levels, achieving area reduction and higher throughput by implementing consensus elements, completion trees, and validity trees with configurable thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional asynchronous logic uses stacks of transistors between power supply rail and ground rail, then logic functionality is achieved, but area efficiency deteriorates and throughput is reduced
Solution Approach 1:
The patent extracts the clock synchronization function from the logic circuit itself and separates it into a global clock circuit that externally controls latch or flip-flop elements. This removes the need for complex transistor stacks within the logic block, reducing area while maintaining throughput through efficient clocked operation.
Solution Approach 2:
The patent segments the logic circuit into combinational logic blocks and storage elements (latches or flip-flops). The combinational logic blocks process data while the storage elements hold state, with each segment optimized independently. This segmentation reduces the area required for each component while maintaining overall circuit throughput through coordinated operation.
2Stability of the object's composition
If synchronous logic uses a global clock circuit to synchronize logic components, then synchronization is achieved, but area efficiency deteriorates due to additional clock circuitry
Solution Approach 1:
The patent merges the clock distribution function into a shared global clock circuit that serves all latch or flip-flop elements across multiple combinational logic blocks. This consolidation provides stable synchronization throughout the circuit while using minimal area compared to individual clock circuits for each logic component.
3Ease of operation
If existing asynchronous logic uses stacks of transistors, then logic operation is enabled, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical transistor stack structure with a clocked architecture using latch or flip-flop elements controlled by a global clock signal. This substitution simplifies the physical structure while maintaining logic operation capability through temporal control rather than spatial stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These circuits operate effectively at lower voltages (less than 1V), achieving a 3× area reduction and 2× higher throughput compared to traditional asynchronous circuits, while allowing for flexible logic functions by adjusting the switching threshold of capacitive input circuits.
Implementation Method 1
capacitive input circuits with linear or nonlinear dielectric materials
Implementation Method 2
capacitive input circuits with linear or nonlinear dielectric materials
Data Source
AI summary
Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.