Low-voltage biasing at the cascode middle node cuts capacitor charging energy during reverse recovery, reducing switch power loss.
Integrated interposer regulators and thermal sensors enable per-sector power-down and DVFS in programmable logic while cutting static power.
Serially coupling semiconductor functional blocks cuts power use and external components, enabling smaller SiP packages and PCB layouts.
Adjustable-threshold capacitive c-elements cut transistor stacking, enabling sub-1V asynchronous logic with smaller area and higher throughput.