Capacitive Consensus Circuits for Low-Voltage Asynchronous Logic
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Solution Overview
Problem
Existing asynchronous logic circuits face challenges in operating efficiently at low voltage conditions due to the need for stacks of transistors between power supply and ground rails, leading to increased power consumption and reduced area efficiency.
Innovation Solution
The development of asynchronous circuits using threshold gates and capacitive input circuits with linear or nonlinear dielectric materials, which reduce the stack of devices and enable operation at lower power supply levels, achieving area reduction and higher throughput by implementing consensus elements, completion trees, and validity trees with configurable thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional asynchronous logic uses stacks of transistors between power supply and ground rails, then logic functionality is achieved, but power consumption increases and area efficiency decreases
Solution Approach 1:
The patent extracts the timing and synchronization function from the transistor stack by introducing a dedicated timing circuit that operates independently. This separates the logic computation function from the timing control function, allowing the main logic path to use fewer transistors while the timing circuit handles synchronization separately.
Solution Approach 2:
The patent introduces a timing circuit as an intermediary component that mediates between the asynchronous logic elements and the clock signal. This timing circuit generates timing signals that coordinate data flow without requiring deep transistor stacks, thus reducing power consumption while maintaining proper synchronization.
2Area of stationary object
If traditional asynchronous logic uses stacks of transistors between power supply and ground rails, then logic functionality is achieved, but area efficiency decreases
Solution Approach 1:
The patent transitions from a vertical transistor stack architecture to a more distributed horizontal architecture where timing functions are performed by separate circuits rather than by stacking transistors vertically. This dimensional change in circuit organization reduces the vertical depth while spreading functionality across more horizontal space, improving area efficiency.
Solution Approach 2:
The patent segments the circuit into distinct functional blocks: timing circuitry for synchronization and logic computation units for data processing. This segmentation allows each block to be optimized independently, reducing the overall transistor stack depth and improving area utilization compared to a monolithic stacked architecture.
3Use of energy by moving object
If asynchronous circuits operate at low voltage levels, then power consumption decreases, but circuit reliability and switching performance deteriorate
Solution Approach 1:
The patent changes the operating parameters of the circuit by introducing timing control signals that optimize the switching behavior at low voltage levels. By carefully controlling the timing and duration of switching events, the circuit maintains reliable operation even with reduced voltage margins, preventing premature failures and ensuring proper logic level transitions.
Solution Approach 2:
The patent implements timing margins and synchronization protocols that provide a cushion against voltage variations and timing uncertainties. By anticipating potential reliability issues at low voltage, the circuit design incorporates sufficient timing margins and validation checks to ensure correct operation even when voltage levels are reduced for lower power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These circuits operate effectively at lower power supply levels, achieving a 3-fold area reduction and 2-fold higher throughput compared to traditional asynchronous circuits, while allowing for flexible logic function implementation by adjusting the switching threshold.
Implementation Method 1
a first capacitor C1 includes a first terminal coupled to the first input and a second terminal coupled to the summing node
Data Source
AI summary
Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.