Capacitive and Inductive Bumps for High-Frequency Signal Integrity
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Solution Overview
Problem
Current microelectronic devices face challenges in high-frequency applications, such as 5G and WiGig communications, due to susceptibility to process variations and inconvenient placement of capacitors for matching and filtering circuits, requiring capacitors with femto Farad and sub-femto Farad capacitance in millimeter wave and sub-THz circuits.
Innovation Solution
The design incorporates capacitive and enhanced inductive bumps with dielectric layers in the micron thickness range, utilizing high permeability materials to create hybrid high-Q filters, combining on-die and off-die components for resonant connections and improved frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitors are used in high-frequency circuits, then capacitance values can be achieved, but the devices are susceptible to process variations and capacitors are not conveniently located for matching and filtering circuits
Solution Approach 1:
The patent merges the capacitor structure with the bump interconnect structure by forming capacitive bumps that integrate both interconnection and capacitance functions. The bump includes a bottom electrode, dielectric layer, and top electrode formed as a single integrated structure, eliminating the need for separate capacitor components and reducing process variation susceptibility.
Solution Approach 2:
The capacitive bump serves multiple functions: it provides electrical interconnection between layers, provides capacitance for high-frequency circuit operation, and can be used for matching and filtering circuits. This multi-functional design eliminates the need for separate capacitor components placed elsewhere on the substrate.
2Quantity of substance
If capacitor size is reduced to achieve femto Farad and sub-fF capacitance, then appropriate capacitance values for mm-wave and sub-THz circuits are achieved, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent achieves precise capacitance control by adjusting parameters such as dielectric layer thickness (micron range), electrode dimensions, and material properties. The capacitance value is controlled by the formula C = εA/d, where the dielectric thickness d and electrode area A are precisely controlled during fabrication to achieve the required fF and sub-fF values.
Solution Approach 2:
The capacitive bump structure allows local optimization of capacitance by varying the dielectric layer thickness and electrode geometry at specific locations. The bottom and top electrodes can be designed with different footprints and the dielectric thickness can be locally adjusted to achieve precise capacitance values for each bump.
3Speed
If high-frequency operation is implemented, then communication speeds are improved, but the quality factor of capacitive bumps decreases
Solution Approach 1:
The patent uses composite material structures in the capacitive bumps, including low-k dielectric materials with specific permittivity values, and combinations of conductive materials for electrodes. The dielectric layer uses materials with optimized permittivity to maintain high quality factor at high frequencies, and the electrode materials are selected for low loss characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality factor of capacitive bumps, reduces susceptibility to process variations, and enables effective filtering and signal transmission in high-frequency applications, supporting frequencies up to 73 GHz and data rates of 1-50 Gbps.
Implementation Method 1
The capacitive bump includes a bottom electrode, a dielectric layer, and a top electrode
Implementation Method 2
utilizing high permeability materials to create hybrid high-Q filters
Implementation Method 3
combining on-die and off-die components for resonant connections and improved frequency operation
Data Source
AI summary
Embodiments of the invention include a microelectronic device that includes a substrate having transistor layers and interconnect layers including conductive layers to form connections to transistor layers. A capacitive bump is disposed on the interconnect layers. The capacitive bump includes a first electrode, a dielectric layer, and a second electrode. In another example, an inductive bump is disposed on the interconnect layers. The inductive bump includes a conductor and a magnetic layer that surrounds the conductor.