Capacitive Isolator Face-to-Face Parasitic Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing capacitive isolators face challenges in minimizing coupling to the node due to wire bonds, leading to large common mode rejection excursions, which can turn into differential voltages, and are costly to produce in high volumes.
Innovation Solution
The solution involves removing wire bonds by placing capacitive elements in face-to-face contact using organic tape or spin-on material, with the capacitive elements being formed on semiconductor dies and positioned to minimize parasitic capacitance, and using adjustable capacitive circuits to match capacitance for improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect chips in horizontal configuration, then electrical isolation can be achieved, but parasitic coupling increases and common mode rejection excursions occur
Solution Approach 1:
The patent removes wire bonds entirely from the system by transitioning to a vertical chip configuration where capacitive coupling occurs through face-to-face contact between chips. This extraction of the harmful wire bond element eliminates the parasitic inductance and unbalanced coupling that caused common mode rejection excursions.
Solution Approach 2:
The patent transitions from a horizontal chip configuration to a vertical configuration, changing the spatial dimension of the arrangement. This dimensional change allows capacitive elements to be positioned in face-to-face contact, reducing parasitic capacitance and improving common mode rejection while maintaining electrical isolation.
2Loss of information
If wire bonds are used for chip connection, then data transmission across isolation boundary is enabled, but signal loss increases due to unbalanced coupling
Solution Approach 1:
By removing wire bonds and replacing them with direct face-to-face capacitive coupling between vertically stacked chips, the patent eliminates the source of unbalanced coupling and associated signal loss. The capacitive coupling provides more symmetric and controlled signal transmission across the isolation boundary.
3Ease of manufacture
If planar package design with wire bonds is used, then production is feasible, but manufacturing cost increases for high-volume production
Solution Approach 1:
The vertical chip configuration enables a stacked package design that reduces the number of wire bonds required and simplifies the interconnection architecture. This dimensional change facilitates high-volume manufacturing by reducing assembly complexity and material costs, making the design more suitable for mass production.
4Reliability
If capacitive elements are positioned close to minimize parasitic capacitance, then common mode rejection improves, but manufacturing precision requirements increase
Solution Approach 1:
The vertical stacking configuration provides a more controlled and standardized method for positioning capacitive elements in face-to-face contact compared to horizontal arrangements. The stacked architecture naturally constrains the relative positioning of chips, reducing the impact of manufacturing tolerances on capacitive coupling balance and common mode rejection performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, minimizes signal loss, and maintains high-voltage isolation ratings while being cost-effective for high-volume production, effectively addressing the common mode rejection issues and improving signal recovery.
Implementation Method 1
The capacitive approach may employ a small capacitor, say 100 fF across the isolation boundary. For the receiver to discern logic level swings differentiated across the isolation boundary, the receiver needs to detect the transmitted signal in the presence of large excursions
Implementation Method 2
the wire bond acts like an antenna with about 1-2 nH of inductance. This inductor is suspended over the isolation boundary and has a certain coupling to the ground planes of both chips. Since most couplers are differential, there are at least two of these wire bonds. If the coupling to these wire bonds is not balanced, then the large common mode rejection excursions (e.g., 1000V at rate of 25,000V/usec) will turn into differential voltages via this unbalanced coupling.
Implementation Method 3
placing capacitive elements in face-to-face contact using organic tape or spin-on material
Data Source
AI summary
A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.