Capacitive Latch Level Shifting Across Multiple Voltage Domains

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing level shifting circuits face challenges in efficiently translating signals across power supply boundaries with different voltage levels, as they often require complex configurations and may not fully utilize the flexibility of power supply voltage differences.

Innovation Solution

A level shifting circuit comprising a clocked latch, second latch, and capacitors, where the clocked latch operates with a first power supply voltage and its complement operates with a second power supply voltage, and the second latch operates with a third and fourth power supply voltage, allowing for AC coupling and voltage level shifting while ensuring safe operating ranges for transistors across different voltage ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional level shifting circuits are used to translate signals across different power supply voltages, then signal level translation is achieved, but the circuit complexity increases and flexibility is reduced

Engineering Contradiction:
Improveflexibility of level shiftingVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The level shifting function is divided into two separate latches operating at different voltage domains. The first latch operates between Vdd1 and Vss1, while the second latch operates between Vdd2 and Vss2. This segmentation allows each latch to be optimized for its specific voltage range, improving adaptability while keeping individual latch complexity low.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Capacitors are used as intermediary elements to couple the output of the first latch to the input of the second latch. These capacitors enable AC coupling that translates voltage levels between different power supply domains without requiring complex direct level shifting circuitry, thus reducing overall circuit complexity while maintaining flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple power supply voltages are used to increase level shifting flexibility, then adaptability improves, but ensuring safe operating ranges for transistors becomes more difficult

Engineering Contradiction:
Improveoperational flexibilityVSAvoidtransistor safety
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Each latch is designed with local quality optimized for its specific voltage domain. The first latch uses transistors sized and configured for safe operation between Vdd1 and Vss1, while the second latch uses transistors optimized for Vdd2 and Vss2. This localized optimization ensures transistor safety in each domain while maintaining overall system flexibility through the voltage translation capability.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If complex level shifting configurations are used to handle different voltage levels, then voltage translation capability is improved, but the ease of operation and implementation is reduced

Engineering Contradiction:
Improvevoltage level translation capabilityVSAvoidease of implementation
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The circuit merges the functionality of voltage level translation with standard latch circuits. By combining the level shifting function with the storage and synchronization functions of latches, the circuit achieves voltage translation capability without requiring separate complex level shifting stages, thereby simplifying implementation while maintaining adaptability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7915921B1Circuits and methods for level shifting a signal
Publication Date: 2011.03.29 MARVELL ASIA PTE LTD
  • US7915921B1 patent drawing
  • US7915921B1 patent drawing
  • US7915921B1 patent drawing

AI summary

In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.