Capacitive Voltage Level Shifter for EOS-Safe Multi-Domain Output

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Solution Overview

Problem

Existing voltage level shifters suffer from electrical overstress (EOS) and time-dependent dielectric breakdown (TDDB) issues, particularly due to the lack of effective voltage shifting for low logical values and the need for additional bias circuits, which are not favored.

Innovation Solution

A voltage level shifter design that uses core transistors and input-output (IO) transistors with thicker gate oxides, incorporating a protection circuit to manage voltage drops and prevent electrical breakdown, and a capacitive coupling mechanism to generate output voltages across multiple domains without static currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing voltage level shifters are used to shift voltage levels, then voltage level shifting is achieved, but transistors suffer from electrical overstress and time dependent dielectric breakdown

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidelectrical overstress and dielectric breakdown
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A protection circuit is introduced as an intermediary between the high voltage domain and low voltage domain transistors. This protection circuit includes transistors that act as mediators to control voltage drops across critical transistors, preventing electrical overstress and dielectric breakdown while allowing voltage level shifting to occur.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the voltage parameters dynamically by using control signals to adjust the voltage drops across protection transistors. By varying the voltage parameters in real-time based on input signal levels, the circuit maintains transistor safety margins while achieving the required voltage level shifting functionality.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a bias circuit is added to provide constant bias to prevent EOS and TDDB, then transistor protection is improved, but device complexity increases

Engineering Contradiction:
Improvetransistor protectionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protection circuit is designed to be self-regulating, using the input signal itself to control the voltage drops across protection transistors. The circuit automatically adjusts its protection level based on the operating conditions without requiring external bias circuits, thereby maintaining reliability while minimizing added complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The protection circuit transistors serve multiple functions: they protect against electrical overstress, prevent dielectric breakdown, and simultaneously enable voltage level shifting. This multi-functionality reduces the need for separate bias circuits and other protective components, keeping the overall device complexity low.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If voltage level shifting is implemented without proper protection, then device complexity is reduced, but harmful factors such as EOS and TDDB increase

Engineering Contradiction:
Improvecircuit simplicityVSAvoidelectrical overstress and dielectric breakdown
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The protection circuit acts as an intermediary layer that adds minimal complexity while effectively blocking harmful voltage spikes. The intermediary transistors are strategically placed to protect critical nodes without requiring complex control logic or additional circuitry, achieving a good balance between simplicity and protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Device complexity

If existing level shifters shift only high logical value voltage levels, then circuit design is simplified, but low logical value voltage levels are not shifted

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidvoltage level shifting capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The protection circuit is designed to handle both high logical value and low logical value voltage levels simultaneously. By using control signals that respond to both voltage levels, the circuit achieves universal voltage level shifting capability while maintaining relatively simple circuit design through shared protection transistors and control logic.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively shifts voltage levels across multiple domains while protecting transistors from electrical breakdown, reducing the risk of EOS and TDDB, and eliminating the need for static currents, thus improving the reliability and efficiency of the voltage level shifting process.

Implementation Method 1

a capacitive coupling mechanism to generate output voltages across multiple domains

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS8854104B2Voltage level shifter
Publication Date: 2014.10.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8854104B2 patent drawing
  • US8854104B2 patent drawing
  • US8854104B2 patent drawing

AI summary

A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.