Capacitive Level Shifter for Metastability-Free Voltage Translation

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Solution Overview

Problem

Level shifters face challenges in interfacing digital circuits with different supply voltage levels, leading to metastability issues due to imbalanced discharging and charging currents, resulting in failed high-to-low transitions and increased leakage in SRAM cells.

Innovation Solution

Incorporating a coupling capacitor in the level shifter circuit to balance currents and stabilize node voltages, ensuring proper high-to-low transitions and eliminating leakage by connecting the capacitor between the input node and the node where metastability occurs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a level shifter interfaces digital circuits with different supply voltage levels, then voltage domain compatibility is improved, but metastability issues occur due to imbalanced discharging and charging currents

Engineering Contradiction:
Improvevoltage domain compatibilityVSAvoidtransition reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

A coupling capacitor is introduced as an intermediary element between the input node and the intermediate node in the level shifter circuit. This capacitor mediates the charge transfer process, ensuring that charging and discharging currents are balanced, thereby preventing metastability issues while maintaining voltage domain compatibility

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the level shifter operates without current balancing, then device complexity is reduced, but leakage increases in SRAM cells

Engineering Contradiction:
Improvecircuit simplicityVSAvoidleakage current
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The coupling capacitor serves as a mediator that balances the charge-discharge cycles in the level shifter circuit. By ensuring equal charging and discharging currents, it prevents the accumulation of charge that would otherwise cause leakage in connected SRAM cells, without significantly increasing circuit complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If the level shifter uses imbalanced currents for fast switching, then switching speed is improved, but node voltage stability deteriorates

Engineering Contradiction:
Improveswitching speedVSAvoidnode voltage stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The coupling capacitor creates a feedback mechanism where the charge stored during the rising edge is discharged during the falling edge. This feedback ensures that the intermediate node voltage returns to its initial state, maintaining stability while allowing fast switching transitions to occur

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The capacitor stabilizes node voltages, ensuring desired high-to-low transitions and eliminating leakage, thereby improving the reliability of level shifting between different voltage domains without affecting the pn ratio.

Implementation Method 1

Incorporating a coupling capacitor in the level shifter circuit to balance currents and stabilize node voltages

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9979399B2Level shifter
Publication Date: 2018.05.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9979399B2 patent drawing
  • US9979399B2 patent drawing
  • US9979399B2 patent drawing

AI summary

A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.