Capacitive Low-Voltage Level Shifter for Sub-Nanosecond Switching
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Solution Overview
Problem
Existing level shifters face limitations in achieving switching times below 0.5 ns and fail at low supply voltages, particularly when VDDL is below 0.75V, due to variability in transistor current driving capability and insufficient peak voltage to fully turn on NMOS transistors.
Innovation Solution
A level shifter design comprising a coupling stage with PMOS transistors and capacitors that generates a switching voltage twice the low voltage power source, allowing faster switching by overdriving NMOS transistors, enabling operation with VDDL as low as 0.75V and achieving switching times significantly faster than prior designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifter designs are used, then the circuit can operate at low voltage, but the switching time cannot be reduced below 0.5 ns due to transistor current driving variability
Solution Approach 1:
The coupling stage generates a switching voltage equal to twice the low voltage power source voltage before the level switching stage operates. This preliminary voltage generation ensures that NMOS transistors receive sufficient gate voltage to fully turn on, eliminating the variability in current driving capability that limits switching speed in conventional designs.
Solution Approach 2:
The invention changes the voltage parameter by generating a switching voltage that is twice the low voltage power source voltage. This parameter change allows NMOS transistors to operate in a fully enhanced region, achieving consistent and fast switching times below 0.5 ns while maintaining low voltage operation.
2Use of energy by moving object
If low voltage power source is used, then power consumption is reduced, but the peak voltage is insufficient to fully turn on NMOS transistors
Solution Approach 1:
The level shifter is divided into two functional stages: a coupling stage that generates the elevated switching voltage, and a level switching stage that performs the actual level conversion. This segmentation allows the low voltage power source to be used for power efficiency while the coupling stage provides the necessary voltage boost to fully turn on NMOS transistors.
Solution Approach 2:
The coupling stage acts as an intermediary that converts the low voltage power source into a switching voltage equal to twice the low voltage. This intermediary stage enables the NMOS transistors to receive sufficient gate voltage to fully turn on, while the overall circuit continues to operate from the low voltage power source, maintaining power efficiency.
3Speed
If faster switching is achieved through voltage boosting, then switching time is reduced, but the circuit complexity increases
Solution Approach 1:
The coupling stage uses PMOS transistors and capacitors to perform multiple functions: generating the elevated switching voltage, providing voltage boosting, and enabling fast switching. This multi-functionality achieves fast switching times while avoiding the need for complex voltage multiplier circuits or additional power supply voltages.
Solution Approach 2:
The invention achieves fast switching by changing the voltage parameter to twice the low voltage power source through the coupling stage. This parameter change enables rapid transistor switching without requiring complex circuit topologies, maintaining relative simplicity while achieving switching times below 0.5 ns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved level shifter achieves switching times at least 3x faster than prior art when VDDL is between 0.75V and 1.26V, while maintaining a simpler design and reduced space requirements on the semiconductor die, effectively overcoming the limitations of previous designs.
Implementation Method 1
A level shifter design comprising a coupling stage with PMOS transistors and capacitors that generates a switching voltage twice the low voltage power source
Data Source
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AI summary
An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.