Capacitively Coupled Logic Gate Reduces Transistor Count
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Solution Overview
Problem
Existing semiconductor logic gate technologies face challenges in efficiently implementing logic functions and memory functions using capacitive coupling, particularly in achieving flexible and efficient implementation of majority functions and dual functionality without significant additional process steps or device count increases.
Innovation Solution
The use of areal capacitive coupling devices that can alter their floating gate potential in response to input signals to generate logic outputs and perform different circuit functions, allowing for the implementation of logic gates with N inputs and memory functions, including majority functions with reduced transistor counts and flexible process compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional logic gate technologies are used, then logic functions can be implemented, but device count and silicon area increase
Solution Approach 1:
The patent merges logic gate functionality and memory functionality into a single device structure. The capacitive coupling device serves both as a logic element and a memory element, eliminating the need for separate logic gates and memory cells. This is achieved by using the floating gate potential to represent both logic states and memory states simultaneously.
Solution Approach 2:
The capacitive coupling device is designed to perform multiple functions: it acts as a logic gate for processing input signals, stores data in memory, and can be configured to perform different logic functions (AND, OR, NAND, NOR, etc.) by adjusting the floating gate potential. This multi-functionality reduces the overall device count in the circuit.
2Productivity
If conventional logic gate technologies are used, then logic functions can be implemented, but silicon area increases
Solution Approach 1:
The patent merges logic gate functionality and memory functionality into a single device structure. The capacitive coupling device serves both as a logic element and a memory element, eliminating the need for separate logic gates and memory cells. This is achieved by using the floating gate potential to represent both logic states and memory states simultaneously.
Solution Approach 2:
The patent utilizes the floating gate potential dimension to encode additional functionality. By controlling the potential of the floating gate, the same physical device can represent different logic states and memory states, effectively adding a functional dimension without increasing physical area.
3Quantity of substance
If capacitive coupling devices are used for logic functions, then device count is reduced, but dual functionality requires additional configuration
Solution Approach 1:
The patent makes the device configuration dynamic by allowing the floating gate potential to be adjusted based on the desired logic function. The device can be reconfigured on-the-fly by changing the potential applied to the floating gate, rather than requiring fixed hardware configurations or additional control circuitry.
4Adaptability or versatility
If areal capacitive coupling is used, then floating gate potential can be altered for logic states, but process compatibility must be maintained
Solution Approach 1:
The patent achieves different logic functions by changing the electrical parameters (potential levels) applied to the floating gate rather than changing the physical structure or material composition. This allows the same device to perform multiple logic functions while remaining compatible with standard CMOS fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient implementation of logic functions with reduced silicon area and device counts, allowing for dynamic behavior adjustment and dual functionality, thereby reducing design and process costs while maintaining compatibility with CMOS logic processes.
Implementation Method 1
a plurality of areal capacitive coupling devices are coupled to process a set of data inputs; each is preferably configured such that a floating gate potential of such device can be altered in response to receiving an input signal from the set of data inputs; the floating gate potential can be adjusted to place the areal capacitive coupling device into a first state or a second state through areal capacitive coupling to a potential associated with a first active region receiving the input signal
Data Source
AI summary
An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.