Reliability Increasing Modifications TRIZ Cases
- CMOS Memory Cell Latchup Prevention via Bus Current Limiting
Bus-mounted current limiters keep parasitic junctions reverse-biased, preventing latch-up without increasing memory cell size or slowing circuit speed.
- Self-Detecting Electronic Connector Using Differential DC Bias
A self-detecting electronic connector uses differential amplifiers and unequal DC biases to identify connection status without dedicated pins.
- Indistinguishable Complementary Bit Cells for Reverse Engineering Protection
Indistinguishable complementary bit cells use differentiated transistor threshold voltages to create secure logic states.
- Voltage Isolation Semiconductor Die Segmentation
Isolation circuitry on one die provides voltage isolation via capacitive coupling to a second die.
- Tamper Resistant IC Using PUF in Passivation Layer
Integrated circuit embeds a physical unclonable function within its passivation layer to detect structural modifications.
- Power Switch Fault Detection Using Dual Storage Circuits
Dual storage circuits capture and compare power switch states to detect always-ON defects, preventing overheating in battery devices.
- Fuse Detection Circuit Using Calibration Signal to Prevent Misjudgment
A fuse detecting apparatus combines an initial result with a calibrating signal via a logical operating unit.
- Isolated Power Rails for Clock Jitter Reduction in Standard Cells
Segmented power delivery isolates high-current clock drivers in a low-resistance second metal layer, reducing voltage drop induced jitter on timing signals.
- Integrated Circuit Asymmetric Threshold Voltage Security
Asymmetric threshold voltages in ICBC-X cells conceal logical states, preventing accurate detection during reverse engineering while reducing area overhead.