Isolated Power Rails for Clock Jitter Reduction in Standard Cells
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Solution Overview
Problem
Integrated circuits face significant clock jitter due to Instantaneous Voltage Drop (IVD) or Dynamic Voltage Drop (DVD) in large drive-strength standard cells, which affects clock signal transport over long distances and induces noise in power meshes, impacting clock frequency and reliability.
Innovation Solution
A standard-cell architecture with dedicated and isolated power rails in lower-noise, lower-resistance metal layers, positioned higher above the substrate, to reduce voltage drop-induced clock jitter, ensuring clock drivers receive power from low-noise power planes through via stacks, thereby isolating them from surrounding power meshes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large drive-strength standard cells are used for efficient clock-signal transport over large distances, then clock signal transport efficiency is improved, but Instantaneous Voltage Drop (IVD) and Dynamic Voltage Drop (DVD) increase causing significant clock jitter
Solution Approach 1:
The power delivery network is segmented into multiple metal layers (first metal layer for standard cell logic gates, second metal layer for clock drivers). This segmentation isolates the high-current clock drivers from the standard cell logic gates, allowing efficient power delivery to clock drivers without inducing voltage drops in the logic gate power mesh, thereby maintaining both transport efficiency and reducing clock jitter.
Solution Approach 2:
The patent transitions from a single-layer power mesh to a multi-layer power delivery architecture. By utilizing a second metal layer positioned at a different height above the substrate, the patent creates a three-dimensional power distribution system that reduces resistance and isolates noise, enabling efficient long-distance clock signal transport while minimizing voltage drops and jitter.
2Device complexity
If power and ground connections of large clock cells are connected to the same metal power mesh as surrounding standard cell logic gates, then device complexity is reduced, but IVD/DVD induced noise affects both clock drivers and surrounding logic gates
Solution Approach 1:
The power mesh is divided into separate segments: a first power mesh in the first metal layer serving standard cell logic gates, and a second power mesh in the second metal layer serving clock drivers. This segmentation prevents noise from clock drivers from affecting logic gates while maintaining a relatively simple overall structure.
Solution Approach 2:
The clock driver power connections are extracted from the standard cell logic gate power mesh and placed in a dedicated second metal layer. This extraction isolates the high-noise clock driver power paths from the sensitive logic gate power mesh, eliminating the mutual interference while adding minimal complexity.
3Manufacturing precision
If metal layers are positioned closer to the substrate, then manufacturing precision is improved, but resistance increases causing higher voltage drop
Solution Approach 1:
The patent utilizes the vertical dimension by positioning the second metal layer for clock drivers at a greater height above the substrate compared to the first metal layer. This three-dimensional arrangement reduces the resistance in the clock driver power paths by increasing the conductor cross-sectional area in the vertical dimension, thereby reducing voltage drops without compromising manufacturing precision.
Solution Approach 2:
The patent changes the physical parameters of the power delivery system by using different metal layers at different heights. The second metal layer, positioned higher above the substrate, has different resistance characteristics that are optimized for high-current clock driver power delivery, reducing voltage drops while maintaining manufacturability.
Data Source
AI summary
A standard cell architecture provides an improved immunity to power-supply voltage-drop, does not induce power-supply voltage drop on a continuous-row power rail of a standard cell, and maintains standard-cell environment compatibility. A circuit includes a first metal layer and a second metal layer that are formed different distances above a substrate. At least one first standard cell drives a first timing signal and includes at least one transistor receiving power from a first power rail in the first metal layer. At least one second standard cell drives a second timing signal and includes at least one transistor receiving power from a second power rail in the second metal layer. The second power rail has both a low peak noise level and a resistance that is lower than that of the first metal layer.