Indistinguishable Complementary Bit Cells for Reverse Engineering Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Reverse engineering of integrated circuits poses a significant threat to the semiconductor industry, as attackers can steal and replicate circuit designs, and existing countermeasures like camouflage circuits are costly and inefficient for mass production.
Innovation Solution
The implementation of Indistinguishable Complementary Bit Cells (ICBC-X) with different threshold voltages for nMOS and pMOS transistors, which are symmetric in layout but respond uniquely to input patterns, making it difficult for attackers to distinguish between logic states and increasing the effort required for reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If camouflage circuits are used to prevent reverse engineering, then security is improved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent applies asymmetry by configuring transistor pairs with intentionally asymmetric threshold voltage relationships. While the physical layout remains symmetric and indistinguishable, the electrical characteristics differ: one transistor in each pair has a higher threshold voltage than its counterpart. This creates functional asymmetry that determines unique logic states without requiring asymmetric physical structures, thereby maintaining security while avoiding the complexity of fully asymmetric camouflage circuits.
Solution Approach 2:
The patent implements local quality by varying threshold voltage characteristics at the transistor level within otherwise identical circuit structures. Each transistor pair maintains the same physical dimensions, layout, and connectivity, but local differences in threshold voltage (achieved through manufacturing variations or intentional doping) create distinct functional behaviors. This allows security to be enhanced through localized electrical property variations rather than global structural complexity.
2Difficulty of detecting and measuring
If threshold voltage variations are used to create indistinguishable bit cells, then reverse engineering difficulty increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes by exploiting threshold voltage as a controllable electrical parameter. Instead of relying on precise geometric dimensions, the invention varies the threshold voltage parameter of transistors within acceptable manufacturing ranges. By comparing threshold voltage relationships (higher vs. lower) rather than absolute values, the system achieves functional differentiation without requiring ultra-precise manufacturing control, thus increasing reverse engineering difficulty while maintaining manufacturing feasibility.
3Ease of manufacture
If symmetric layout is used for transistor pairs, then manufacturing ease is improved, but security against reverse engineering deteriorates
Solution Approach 1:
The patent introduces threshold voltage relationship as an intermediary property that mediates between symmetric physical layout and functional differentiation. The symmetric layout serves as the physical intermediary structure, while the threshold voltage relationship (higher/lower) acts as the functional intermediary that provides security. This two-level approach allows the physical structure to remain simple and manufacturable while the electrical characteristics provide the necessary security against reverse engineering.
Data Source
AI summary
A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.