Master Chip Impedance Control for Multi-Chip Semiconductor Packages
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Solution Overview
Problem
Current semiconductor packages lack the ability to freely control and set termination impedance values for both master and slave chips, limiting flexibility and compatibility with conventional controller chips.
Innovation Solution
Incorporating a master chip with storage and impedance control circuits to manage impedance settings for both itself and slave chips, allowing for impedance matching and generation of combined impedance values for simultaneous termination operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each chip in the package has its own termination circuit with independently controllable impedance settings, then the impedance control flexibility is improved, but the device complexity increases
Solution Approach 1:
The patent consolidates multiple termination circuits into a single termination circuit located in the master chip. This master termination circuit can control impedance for both the master chip and slave chips simultaneously, reducing the total number of termination circuits from multiple individual circuits to one shared circuit, thereby simplifying package structure while maintaining impedance control flexibility
Solution Approach 2:
The master chip's termination circuit is designed to serve multiple functions: it can terminate impedance for the master chip itself and also terminate impedance for one or more slave chips. This multi-functional design allows a single circuit to replace multiple dedicated termination circuits, reducing complexity while preserving adaptability
2Measurement precision
If multiple chips perform termination operations simultaneously with different impedance settings, then the impedance matching accuracy for individual chips is improved, but the overall system reliability deteriorates due to parallel impedance interaction
Solution Approach 1:
The patent implements selective termination control where the master termination circuit applies different impedance settings to different chips based on their individual needs. The controller can enable termination for specific slave chips while keeping other slave chips or the master chip in high-impedance state, allowing precise local impedance matching without unwanted parallel interactions
Solution Approach 2:
The termination circuit implements dynamic control where impedance settings can be changed in real-time based on operational requirements. The controller can dynamically enable or disable termination for specific chips during operation, allowing the system to adapt impedance configurations dynamically rather than being fixed, thereby maintaining reliability while achieving accurate impedance matching when needed
3Ease of operation
If the package uses a conventional controller chip interface without master chip impedance management, then the ease of operation with conventional controllers is improved, but the adaptability to multi-chip configurations deteriorates
Solution Approach 1:
The master chip acts as an intermediary between the conventional controller chip and the slave chips. It manages impedance termination for the entire package including both itself and slave chips, while presenting a standard interface to the conventional controller. This intermediary role allows conventional controllers to operate with multi-chip packages without modification, while still achieving proper impedance matching through the master chip's coordination
Data Source
AI summary
A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip.