Receiver Circuit Common Mode Control and Signal Observation

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Solution Overview

Problem

Conventional differential serial data receivers experience signal integrity issues due to non-ideal common mode termination, leading to signal degradation from reflections, especially in high-speed serial communications.

Innovation Solution

A serial data receiver circuit with a common mode control circuit providing a zero output impedance and a selection circuit for test mode operations, allowing for ideal common mode termination and reduced loading on differential inputs, using a combination of differential transistor pairs and operational amplifiers for effective signal observation and termination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional differential serial data receivers are used without integrated common mode control, then device complexity is reduced, but signal integrity deteriorates due to non-ideal common mode termination and reflections

Engineering Contradiction:
Improvesignal integrityVSAvoidreceiver circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the common mode control circuit and termination circuit directly into the receiver input stage, merging multiple functions (common mode termination, differential signal reception, and impedance matching) into a single integrated structure. This eliminates the need for separate external components while maintaining signal integrity through ideal common mode termination.

Inventive Principle:
Principle #5Merging (Combining)

2Difficulty of detecting and measuring

If additional probe pads are added for observing internal clock and control signals, then measurement capability is improved, but device complexity and area increase

Engineering Contradiction:
Improvesignal observation capabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The differential input nodes are designed to serve dual purposes: their primary function of receiving differential serial data signals and a secondary function of outputting internal clock and control signals for observation. This multi-functionality eliminates the need for separate probe pads or test nodes, allowing signal observation without adding extra components or increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of adding separate observation points (probe pads) to monitor internal signals, the patent inverts the approach by making the existing differential input nodes capable of both receiving external signals and outputting internal signals. This reversal of the traditional observation method allows measurement capability to be achieved without increasing device structure.

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If the common mode node is left floating or poorly terminated, then device complexity is minimized, but signal integrity deteriorates due to common mode signal reflections

Engineering Contradiction:
Improvesignal integrityVSAvoidtermination circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The common mode control circuit automatically detects and adjusts the common mode voltage level at the common mode node to maintain optimal termination conditions. This self-regulating mechanism ensures ideal common mode termination and prevents reflections without requiring external adjustment or complex manual intervention, achieving signal integrity through the circuit's own internal control.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7315182B2Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control
Publication Date: 2008.01.01 TEXAS INSTRUMENTS INC
  • US7315182B2 patent drawing
  • US7315182B2 patent drawing
  • US7315182B2 patent drawing

AI summary

A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.