On Die Termination Control via Clock Toggle Comparison
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Solution Overview
Problem
Conventional on die termination (ODT) control methods fail to synchronize the operation of the ODT circuit with the external clock signal across varying frequencies, leading to potential signal transmission failures due to impedance mismatching and delayed activation of the ODT circuit.
Innovation Solution
A control apparatus and method that includes a counting unit for receiving external and DLL clock signals, comparing the toggle numbers of both signals, and generating an ODT enable signal based on the comparison to ensure timely activation of the ODT circuit, independent of frequency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a predetermined delay time is fixed for ODT circuit activation, then the ODT circuit can be simply controlled, but the ODT circuit cannot operate at the desired timing under high frequency operations
Solution Approach 1:
The patent applies dynamics by making the delay time variable rather than fixed. The delay time is dynamically adjusted based on the frequency of the external clock signal, allowing the ODT circuit to activate at the correct timing regardless of whether the system operates at low or high frequencies. This resolves the contradiction by adapting the control parameter to operating conditions.
Solution Approach 2:
The patent changes the parameter of delay time based on frequency conditions. When the external clock signal frequency exceeds a reference frequency, the delay time is set to a first value; otherwise, it is set to a second value. This parameter adjustment ensures reliable ODT operation timing across different frequency ranges while maintaining manageable control complexity.
2Reliability
If the ODT circuit is activated later than desired timing, then the clock domain difference between DLL clock and internal clock is not properly managed, but the fixed delay control is simpler to implement
Solution Approach 1:
The patent changes the delay parameter based on frequency to ensure proper clock domain synchronization. By setting different delay values for different frequency ranges, the system maintains accurate timing relationships between the DLL clock and internal clock without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The patent introduces a frequency detection unit and control unit as intermediaries between the external clock signal and the ODT circuit activation. These intermediary components analyze the frequency and generate appropriate delay control signals, simplifying the overall control logic while ensuring reliable clock domain synchronization.
3Device complexity
If external fixed resistors are used for impedance matching, then the impedance matching circuit is simpler, but the impedance matching deteriorates due to aging, temperature variation and manufacturing process variation
Solution Approach 1:
The patent applies dynamics by making the termination resistance adjustable rather than fixed. The impedance matching circuit dynamically changes its resistance value based on operating conditions such as temperature and aging, ensuring consistent impedance matching accuracy throughout the device lifecycle while maintaining a relatively simple circuit structure.
Solution Approach 2:
The patent changes the resistance parameter of the termination resistor based on operating conditions. By adjusting the resistance value in response to temperature variation and aging effects, the system maintains accurate impedance matching without requiring a complex circuit topology, thus resolving the contradiction between simplicity and reliability.
Data Source
AI summary
An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.