Power Gating Control System for Logic Circuit Signal Retention
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Solution Overview
Problem
Semiconductor apparatuses using zigzag power gating schemes may experience operational issues due to slight differences in the sequence of header and footer transistors, leading to abnormal logic circuit operation or increased leakage current, especially when power gating circuits are not appropriately designed.
Innovation Solution
A semiconductor apparatus with a power gating control system that tests the logic circuit's output signal when the power gating circuit is turned off, generating a gating control signal based on the test result and operation mode to ensure proper power supply voltage application, and includes a repair method to maintain power supply to logic circuits during standby operations if the power gating circuit is inappropriately designed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power gating circuit is turned off during standby operation, then power consumption is reduced, but the logic circuit may not retain its output signal properly due to inappropriate design
Solution Approach 1:
The patent applies preliminary action by testing the logic circuit's ability to retain output signals before finalizing the power gating control strategy. The power gating control system performs a test by turning off the power gating circuit and checking whether the logic circuit maintains its output signal. Based on this preliminary test result, the system decides whether to enable power gating during standby operation, thus preventing potential signal retention issues while achieving power savings.
2Reliability
If the power gating circuit is designed to always apply power supply voltage to logic circuits, then the logic circuits operate normally, but power consumption increases during standby operation
Solution Approach 1:
The patent applies dynamics by making the power gating control strategy adaptive rather than static. The power gating control system dynamically adjusts its behavior based on test results and operation modes. When the logic circuit passes the retention test, the system enables dynamic power gating during standby operation. When the test fails, the system dynamically switches to a mode that maintains power supply, thus optimizing the balance between reliability and power consumption based on actual circuit behavior.
Solution Approach 2:
The patent applies parameter changes by modifying the power gating control parameters based on test results. The system changes the gating control signal generation logic depending on whether the logic circuit retains output signals properly. This parameter adjustment allows the system to switch between aggressive power gating (when retention is reliable) and conservative power gating (when retention is unreliable), optimizing both power consumption and reliability.
3Device complexity
If the zigzag power gating scheme uses header and footer transistors with slight sequence differences, then device complexity is reduced, but leakage current increases or logic circuits do not operate normally
Solution Approach 1:
The patent applies feedback by using the output signal retention test results to adjust the power gating control strategy. The power gating control system monitors whether the logic circuit properly retains its output signal after power gating is applied, and uses this feedback information to determine future power gating operations. This closed-loop feedback mechanism allows the system to adapt to slight variations in transistor sequencing and prevent leakage current issues by adjusting control parameters based on actual circuit behavior.
Data Source
AI summary
A semiconductor apparatus may include a logic circuit, a power gating circuit and a power gating control system. The logic circuit may operate by receiving a first power supply voltage and a second power supply voltage, and may retain an output signal at a predetermined logic value during a standby operation of the semiconductor apparatus. The power gating circuit may apply the first power supply voltage and the second power supply voltage to the logic circuit when a gating control signal is in an enabled state. The power gating control system may test whether the output signal of the logic circuit retains the predetermined logic value when the power gating circuit is turned off, and may generate the gating control signal based on a test result and an operation mode of the semiconductor apparatus.