Integrated Circuit Asymmetric Threshold Voltage Security
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to reverse engineering, which can lead to unauthorized reproduction and misuse, particularly in security-related applications, and existing protection methods like camouflage circuits are costly and energy-intensive.
Innovation Solution
Incorporating Indistinguishable yet Complementary Bit-Cells (ICBC) with password-protected Boolean secrets, where the ICBC-X instances have different threshold voltages for nMOS and pMOS components, making it difficult to distinguish between logical states through standard reverse engineering methods, and using key-lock gates to securely access these secrets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard reverse engineering methods are used to analyze IC circuits, then circuit design can be extracted and cloned, but security protection is compromised
Solution Approach 1:
The patent applies asymmetry by using different threshold voltages for nMOS and pMOS transistors in ICBC-X instances. This creates asymmetric voltage behavior where the circuit responds differently to high and low voltage inputs, making it impossible to determine logical states through standard voltage measurement reverse engineering methods, thereby enhancing security protection while maintaining circuit functionality
Solution Approach 2:
The patent changes the voltage parameter characteristics by implementing ICBC-X cells with non-standard threshold voltage relationships. Instead of conventional symmetric threshold voltages, the circuit uses asymmetric threshold values that cause the circuit to operate in a metastable region, preventing accurate logical state detection and significantly increasing the difficulty of reverse engineering analysis
2Reliability
If camouflage circuits are used to protect ICs from reverse engineering, then security is improved, but area consumption and energy usage increase
Solution Approach 1:
The patent implements multi-functionality by designing ICBC-X instances that simultaneously serve as both functional logic elements and security protection mechanisms. The same circuit cells perform computational functions while their asymmetric voltage characteristics provide inherent resistance to reverse engineering, eliminating the need for separate camouflage circuits and reducing overall area consumption
Solution Approach 2:
The patent merges the security protection function with the functional logic circuitry by integrating asymmetric threshold voltage characteristics directly into the logic cell design. This combination creates a unified structure where security and functionality coexist in the same circuit elements, avoiding additional area overhead from separate protection circuits
3Reliability
If camouflage circuits are used to protect ICs from reverse engineering, then security is improved, but energy consumption increases
Solution Approach 1:
The patent implements multi-functionality by designing ICBC-X instances that simultaneously serve as both functional logic elements and security protection mechanisms. The same circuit cells perform computational functions while their asymmetric voltage characteristics provide inherent resistance to reverse engineering, eliminating the need for separate camouflage circuits and reducing overall area consumption
Solution Approach 2:
The circuit provides self-service security protection through its inherent asymmetric voltage characteristics without requiring additional active protection mechanisms. The ICBC-X cells automatically resist reverse engineering attempts through their metastable operation region, eliminating the need for extra energy-consuming security subsystems
Data Source
AI summary
According to various embodiments, an integrated circuit is described comprising a plurality of subcircuits having different signal transfer reaction times, a control circuit configured to form two competing paths from the plurality of subcircuits in response to a control signal, an input circuit configured to supply an input signal to the two competing paths and an output circuit configured to generate an output value depending on which of the competing paths has transferred the input signal with shorter reaction time.